Good morning,

does anyone have a PCI bridge interfaced to Nios or NiosII
processor's bus?

If yes, how difficult is to connect Altera's embedded core to a WBC
peripheral?

Thanks all,
Paolo

I'm implementing OpenCores PCI IP Core into a system based on Nios II. It's not difficult if you don't need streaming transfers, as WB and Avalon interfaces are very similars. Now I'm simulating streaming transfers and it seems that my implementation works. -You have to take into account Avalon address shifts for external devices (read carefully "Avalon Bus Spec's Reference Manual" pag 100) -you must create both write and read avalon signals from WB write enable signal -You can assign wbs_ack_o to avs_waitrequest_n All other signals have same meanings or very similar. If what you want is an Avalon Streaming Slave, you will need a FIFO in your wrapper and use fifo control signals (like empty, almost_empty, full) to implement streaming signals(avs_dataavailable, avs_dataready, avs_endofpacket). In case you want to implement PCI Core you can use "wbw" and "wbr" fifo's control signals. paolo.morgano@teamware.it wrote:

Yes, it works quite nicely.



It's not very difficult ... the two are very similar.

Plan on using the bridge to access on-chip memory/registers or
high-speed external memory though. If you use the standard
altera SDRAM controller you may be disappointed -- it is
__very__ slow.

Regards,
--Scott