Hi,
IÂ’m new to the PCI bus. I have been working with your core now for a
couple of weeks now and have some questions. I have been using your
tool to configure the PCI Bridge (PCIBridgeConfig.exe) for my project.
I’m trying to create a simple PCI target device so I select “Guest-
Bridge” and then “Target only”. This creates a definition in
the “pci_user_contrants.v” file called “TARGET_ONLY”. My problem is
that I donÂ’t understand how this definition is being used. I did a search
though all the files and could not see how it was being implemented.
Also, I could not find it mentioned in the documents supplied with this
core.

A similar problem was noticed with the definition “ADDR_TRAN_IMPL”.
While this could be found in the documents, I was unable to find any
verlog file that used it other than being defined in
the “pci_user_contrants.v” file.

So what am I missing?

An observation. I think the configuration tool is great for people like me
that are new to PCI, but it looks like it needs to be updated a little. The
changes made last July defining SubsystemVendorID, SubsystemID,
MAXLatency, MinGnt need to be added to this tool. Also, I noticed that
when the tool creates the “pci_user_contrants.v” file, PCI_AT_EN# and
WB_AT_EN# are defined with a value of “20'hN_” or “20’hY_” instead
of “1'b0” or “1’b1” and WB_BA# is defined with a nothing. WB_BA#
should be defined with something like 20'h0000_0 as a default.

Anyhow, IÂ’ve been pouring though this IP core before asking for help in
understanding this core. This is also my first time using Wishbone and I
prefer it over the Avalon bus from Altera. Good choice on this. So if I
could get some advice on a simple PCI target, I would greatly
appreciate it.

Thanks,
Nick