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Base Address Register
by Unknown on Jun 7, 2005 |
Not available! | ||
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Hi,
I need help in understanding how the BAR is set for the PCI images in a Guest configuration. Currently I'm able to view the PCI Configuation registers, which shows all six BARs set to zero. Who is suppose to set the BARs on my device? Is it the Host-Bridge? Am I suppose to set the BARs from the wishbone side? In my pci_user_constants.v file, I only see the base address being set on the wishbone side. Why is there no means to set the base address on the PCI side? Since I'm using this PCI IP core to simply control registers on the Wishbone side from the PCI side, I have no processor on the Wishbone side to configure any registers. Is the Wishbone side expected to configure the base address on the PCI images? Thanks in advance, Nick |
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Base Address Register
by Unknown on Jun 7, 2005 |
Not available! | ||
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Your BARs should be set by the host (if you are using the guest
configuration) during PCI enumeration.
On 6/7/05, npd at aps.anl.gov npd at aps.anl.gov> wrote:
Hi,
I need help in understanding how the BAR is set for the PCI images in
a Guest configuration. Currently I'm able to view the PCI Configuation
registers, which shows all six BARs set to zero. Who is suppose to set
the BARs on my device? Is it the Host-Bridge? Am I suppose to set the
BARs from the wishbone side?
In my pci_user_constants.v file, I only see the base address being set
on the wishbone side. Why is there no means to set the base address on
the PCI side?
Since I'm using this PCI IP core to simply control registers on the
Wishbone side from the PCI side, I have no processor on the Wishbone
side to configure any registers. Is the Wishbone side expected to
configure the base address on the PCI images?
Thanks in advance,
Nick
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
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