First of all, i would like to make a short brief about myself. My name is
calvin tan from malaysia. Now process my electronic degree in the
universtity. this sem our pro assign us a project regarding the pci. this
project must using chip 8255 to complete. it mean i am going to deal a
8 bits simple pci card. i hope somebody here could help me.

1.my question is how the pci slot going to detect the pci card, because
our normal pc there will be some other pci card like sound card,lan card.
in order to avoid some conflict, what should i do???

2.inside my design, do i need any card identification block???if yes
please list it out for me.

In is impossible to use 8255 in any PCI design. ----- Original Message ----- From: chtan82 at yahoo.com> To: pci at opencores.org> Sent: Sunday, July 17, 2005 9:54 AM Subject: [pci] how the pci slot going to detect the pci card???

I would agree that the 8255 is impractical for any PCI design for real
world use, but for a Unv project it may be OK.

Put a side the limitations of the 8255, is the Opencores PCI IP core
unable to control such a simple device if the core was configured as a
GUEST where the PCI side would just write and read the 8255? I believe a
simple wishbone slave interface for the 8255 should be all that is
needed for this project. Please correct me if I'm wrong, I may not fully
understand this PCI core.

Calvin, all PCI devices must have a configuration register block which
is used to configure the PCI device during a power-up cycle or a system
reset. I would recommend a book titled "PCI System Architecture", which
should help with understanding how the device is mapped on the PCI bus
by using this configuration block. Also, I would recommend that you
download Wishbone spec plus all of the Opencore documentation for the
PCI core.

This PCI core from Opencores should work as a simple PCI target if you
set it up correctly, but it will require a little more work to disable
the PCI master controller in this core to accomplish this. I have not
done this myself, so I can't show you exactly how to do it at the
moment. Maybe someone on this forum may confirm or deny this statement,
that is, that this core can be used as a PCI target only core.

Nick

Wojciech Cynk ARCO wrote:

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Nicholas DiMonte wrote:

Why would you need to disable the master unit??? If there's nothing driving the master unit, then it won't interfere at all. If you configure the core in GUEST mode, define the device/vendor ID and the required memory or I/O spaces, it will simply appear on the bus, configured by the PC's BIOS. I'd suggest using something like CDBG to communicate with the target in the early stages. If it hasn't already got one, you'd need to provide a wishbone interface to the 8255 (I'm not clear whether this is a 'real world' IC you intend using or a soft-core version). In any case, there's not a lot of work to do here. As someone suggested, download the PCI and WISHBONE specs. Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

I am by no means a PCI expert, but would like to share my learning
experience trying to create a PCI target-only device using this core in
a Altera FPGA.

If you don't disable the PCI master, then it will not allow the Host on
the PCI bus to configure the PCI side of the GUEST bridge. With my
Altera application this was simply done by grounding some wishbone slave
input signals that initiate a PCI master cycle. Just leaving them float
caused me trouble in Altera.

I'm sorry if I gave the impression that the core had to be modified to
accomplished this. I myself have been struggling with my Altera
application trying to get the FIFO's to work when I discovered the
problem above for my target-only device. The fix above allowed the BIOS
to configure the PCI configuration registers. Now I have a properly
configured core with two BAR's being defined. My only problem seems to
be with the Altera RAM's not being configured correctly. Once this is
solved I will be a happy camper.

What is a CDBG?

Nick



Mark McDougall wrote:

Nicholas DiMonte wrote:



PCI mastering has absolutely nothing to do with who configures the core.
If the core is built as a GUEST bridge, then the configuration of the
core is done by another entity on the PCI bus.

PCI mastering is the ability to *initiate* a transaction on the PCI bus.



Perhaps with 'floating' inputs to the PCI master unit, it was preventing
the PC host from grabbing the bus to initiate config cycles for the core?

http://www.probo.com/cdbg.htm> Invaluable for bringing up and debugging PCI designs. Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

I never suggested that PCI mastering had anything to do with who
configures the core. I will try to be a little more clearer as to what I
experienced.

By not grounding the WB slave unit of the core for target-only
applications, the WB slave unit was trying to execute a PCI cycle when a
PCI host was trying to read and configure the WB PCI side. The PCI host
was never able to read the PCI configuration registers, much less
configure them, due to the core wanting to do its own PCI master cycle.
I had no clue why the BIOS would not configure the PCI core until I
turned on the internal logic analyzer of the FPGA and started to trace
the internal signals of the core. I discovered that the PCI target-unit
would acknowledge configuration commands from the host, but since the
core wanted to do its own PCI cycle at the same time, the core would not
pass any configuration data back to the host. Hence, the PCI host was
never able to configure the core. All because the core was trying to
execute its own PCI master cycle. By grounding the WB slave input
control signals, the internal contention in the core was removed and the
PCI host was able to configure the core.

I hope this helps all that try to use this core as a target-only core.

Nick

Mark McDougall wrote: