Hi, Sorry for bother. I am trying to implement the PCI core on a Spartan II 2s200 PCI Board from Memec. In my design I eliminated everything related to the wishbone side from the top.v module and loaded the FPGA. The computer recognized the pci bridge with the lspci command . Now I am trying to implement the Simple General Purpose IO core, which is very simple and compatible with Wishbone and you can download it from here: http://www.opencores.com/cvsweb.shtml/simple_gpio/rtl/ I am trying to learn how Wishbone works. My questions are: Is this simple_gpio.v file a top file? or I should include its code in my top.v code which also have the PCI IOB definitions? I should LOC the simple_gpio defined wishbone pins? I am confused with the Wishbone part. Thanks for your help. Regards, Jorge

jtrabal at engin.umass.edu wrote: You have tryied the pci core as is, so it was the top entity. At now, you must do a new top entity which will include the pci core and simple io core. Then you LOC the io simple port signals and the pci signals. The wishbone signals are connected between pci core and simple io port core but you will not connect them to any pin. Best regards, -- Técnico Andrés Trapanotto INSTITUTO NACIONAL DE TECNOLOGÍA INDUSTRIAL Centro de Investigación Telecomunicaciones, Electrónica e Informática Teléfono (54 11) 4724 6300 Interno 6362 andres_t at inti.gov.ar ___________________________________________ 0800 444 4004 | www.inti.gov.ar