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Some Warnings
by Unknown on Aug 11, 2005 |
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Hi,
Sorry for bother you again. I am trying to implement the PCI Core with
the simple_gpio core, which can be found in the following address:
http://www.opencores.com/projects.cgi/web/simple_gpio/overview
I LOC the GPIO I/O pins (which are inout signals) to the FPGA pins using
the following;
NET "GPIO[1]" LOC = "V12" ;
But when I synthesize, the following warnings occur:
WARNING:NgdBuild:470 - bidirect pad net 'GPIO' has no legal driver
and
WARNING:Par:276 - The signal GPIO_IBUF has no load
Any help with those warnings? I have to define anything more
than "inout [8:1] GPIO" right? Where in the master Wishbone I have to
connect the 8 GPIO pins? Thanks
Regards,
Jorge
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Some Warnings
by Unknown on Aug 12, 2005 |
Not available! | ||
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On 08/11/2005 12:10 PM, jtrabal at engin.umass.edu wrote:
Hi,
Sorry for bother you again. I am trying to implement the PCI Core with
the simple_gpio core, which can be found in the following address:
http://www.opencores.com/projects.cgi/web/simple_gpio/overview
I LOC the GPIO I/O pins (which are inout signals) to the FPGA pins using
the following;
NET "GPIO[1]" LOC = "V12" ;
But when I synthesize, the following warnings occur:
Out of curiousity, what software are you using? The Xilinx ISE or Webpack? Jeff |
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