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GPIO Core
by Unknown on Aug 16, 2005 |
Not available! | ||
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Hi,
Sorry for bother. I am trying to implement the PCI core on a
Spartan II 2s200 PCI Board from Memec. Also, I am trying to implement
the Simple General PurposeIO core, which is very simple and compatible
with Wishbone andcan be downloaded from here:
http://www.opencores.com/cvsweb.shtml/simple_gpio/rtl/
I only need output pins. In the header of the simple_gpio.v file says the
following (I copy here from there):
// Registers:
//
// 0x00: Control Register
// bits 7:0 R/W Input/Output '1' = output mode
// '0' = input mode
// 0x01: Line Register
// bits 7:0 R Status Current GPIO pin level
// W Output GPIO pin output level
//
// Use a pin as an output:
// Program the corresponding bit in the control register to 'output mode'
('1').
// Program the GPIO pin's output level by writing to the corresponding
bit in the Line Register.
// Reading the GPIO pin's Line Register bit while in output mode returns
the current output level.
My questions are:
1) How can I program the corresponding bit in the control register
to 'output mode' ('1')?
2) How can I program the GPIO pin's output level by writing to the
corresponding bit in the Line Register?
Is that can be done only changing:
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
ctrl
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GPIO Core
by Unknown on Aug 17, 2005 |
Not available! | ||
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jtrabal at engin.umass.edu wrote:
My questions are:
(Verilog code snipped)
No! The idea is to program the I/O pin from the host software! Once
everything has been hooked up to the wishbone bus, you configure the
image in the FPGA and then you can write to the registers using software
on the host (PC?) to talk via the BAR memory / I/O space. This is how
you select the input or output mode of each pin.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
1) How can I program the corresponding bit in the control register to 'output mode' ('1')? 2) How can I program the GPIO pin's output level by writing to the corresponding bit in the Line Register? |
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GPIO Core
by Unknown on Aug 17, 2005 |
Not available! | ||
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Does anyone have any experience using JTAG interface on the Xilinx Spartan -3 Starter kit?
I am having trouble with the JTAG communication between my laptop and the proto-type
card? It can't see the FPGA or serial PROM
Will appreciate any advice
thx
Tim Burroughs
mailto:tburroughs at northropgrumman.com
-----Original Message-----
From: pci-bounces at opencores.org [mailto:pci-bounces at opencores.org]On
Behalf Of Mark McDougall
Sent: Tuesday, August 16, 2005 8:16 PM
To: Discussion list about free, open source PCI IP core
Subject: Re: [pci] GPIO Core
jtrabal at engin.umass.edu wrote:
My questions are:
(Verilog code snipped)
No! The idea is to program the I/O pin from the host software! Once
everything has been hooked up to the wishbone bus, you configure the
image in the FPGA and then you can write to the registers using software
on the host (PC?) to talk via the BAR memory / I/O space. This is how
you select the input or output mode of each pin.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
1) How can I program the corresponding bit in the control register to 'output mode' ('1')? 2) How can I program the GPIO pin's output level by writing to the corresponding bit in the Line Register? |
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GPIO Core
by Unknown on Sep 26, 2005 |
Not available! | ||
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I do not have a Xilinx PCI dev board, but I have an AvNET PCI dev board.
The board is similar in functionality. I can not tell for sure for your Xilinx board, but on the AvNET board, you have to change some jumpers to make the PCI interface part of the chain. This make the board accessible via JTAG through the JTAG port of the board (through the JTAG interface header pins of the board) as default. Those are soldered jumpers (zero-ohm resistors). I would suspect something similar may be present on the Xilinx board. You should check with the user guide of the dev board. If you can see, from the PC, all the interfaces on your conputer, but not the dev board, it is likely that the dev board simply bypass JTAG (send the PCI TDI pin directly to PCI TDO pin). Some soledering could do the trick. Eric
From: "Burroughs, Timothy D." timothy.burroughs at ngc.com>
Reply-To: "Discussion list about free, open source PCI IP core"
pci at opencores.org>
To: "Discussion list about free, open source PCI IP core"
pci at opencores.org>
Subject: RE: [pci] GPIO Core
Date: Wed, 17 Aug 2005 11:48:05 -0500
Does anyone have any experience using JTAG interface on the Xilinx Spartan
-3 Starter kit?
I am having trouble with the JTAG communication between my laptop and the
proto-type
card? It can't see the FPGA or serial PROM
Will appreciate any advice
thx
Tim Burroughs
mailto:tburroughs at northropgrumman.com
-----Original Message-----
From: pci-bounces at opencores.org [mailto:pci-bounces at opencores.org]On
Behalf Of Mark McDougall
Sent: Tuesday, August 16, 2005 8:16 PM
To: Discussion list about free, open source PCI IP core
Subject: Re: [pci] GPIO Core
jtrabal at engin.umass.edu wrote:
> My questions are:
(Verilog code snipped)
No! The idea is to program the I/O pin from the host software! Once
everything has been hooked up to the wishbone bus, you configure the
image in the FPGA and then you can write to the registers using software
on the host (PC?) to talk via the BAR memory / I/O space. This is how
you select the input or output mode of each pin.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
> > 1) How can I program the corresponding bit in the control register to > 'output mode' ('1')? > > 2) How can I program the GPIO pin's output level by writing to the > corresponding bit in the Line Register? |
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