Im trying to implement PCI 33Mhz 3.3v 32bit

I would like to get some advice and help for my project for building a
PCI bridge using the open core PCI and Altera's EPM1270t144C3 (Max II
CPLD).
Im confused as I get many warnings something like 1400 warnings,
mainly the errors are:

Warning: Verilog HDL assignment warning at pci_wbw_wbr_fifos.v(580):
truncated value with size 32 to match size of target (3)

Warning: No clock transition on register
"pci_bridge32:bridge|pci_conf_space:configuration|set_pci_err_cs_bit8"
due to stuck clock or clock enable

Warning: Reduced register
"pci_bridge32:bridge|pci_conf_space:configuration|set_pci_err_cs_bit8"
with stuck clock port to stuck value GND

Please let me know what I should do about the warnings.

I would also like to learn about the constrains needed.

I would be very obliged if you can help me by your valuable advice

Regards
Rajan