I've been working on interfacing the PCI core to A TI 671x EMIF bus
via a WB master interface. I've encountered a slight issue in the way
the [ACK_O] signal is handled in the slave unit.

This is what IÂ’m observing in hardware. I start a cycle by asserting
[CYC_O], [STB_O] and[ WE_O] and qualify [ADR_O]. The slave unit
responds after a few clock cycles with an [ACK_O] that looks to be
sync with [CLK_I]. Since the WB Master samples [ACK_I] on the rising
edge of [CLK_I] the signal [ACK_I] (due to delay) is not qualified
until the following cycle.

The problem is that the Slave unit negates the [ACK_O] signal at the
end of the current clock cycle even though the Master is still
asserting [CYC_O] and [STB_O]. My understanding of the WB B3 spec,
the slave should continue to assert [ACK_O] until [CYC_O] or [STB_O]
are negated.

Is this a correct observation of the [ACK_O] signal from the slave?

Further more, the slave enters a second read cycle which is the
terminated from the previos master read cycle. The problem here is
that [ACK_O] remains asserted. Not a problem for the Master, but the
slave is not ready and the cycle is terminated too early.

I'm going to look into correcting this by these methods
1) the slave unit continues to assert [ACK_O] untill [STB_I] is nagated.
2) the slave unit asserts ack before rising edge of the qualifiing
edge of [CLK_I]


Paragraphs from WB B3 spec:

3.1.3 Handshaking Protocol
All bus cycles use a handshaking protocol between the MASTER and SLAVE
interfaces. As
shown in Figure 3-2, the MASTER asserts [STB_O] when it is ready to
transfer data. [STB_O]
remains asserted until the SLAVE asserts one of the cycle terminating
signals [ACK_I], [ERR_I]
or [RTY_I]. At every rising edge of [CLK_I] the terminating signal is
sampled. If it is asserted,
then [STB_O] is negated. This gives both MASTER and SLAVE interfaces
the possibility to
control the rate at which data is transferred.