1/1 
|
Xilinx "jlbl.v" file
by Unknown on Nov 21, 2005 |
Not available! | ||
|
Hi,
I was reading the old pci forum e-mails and I found the following: /////////////////////////////////////////////////////////////////////// Just to remind you, if you didn't do that already: If you define PCI_XILINX_DIST_RAM and WB_XILINX_DIST_RAM, you also have to define PCI_RAM_DONT_SHARE and WB_RAM_DONT_SHARE, since distributed RAM cannot be shared between two FIFOs - It only has one write and one read port. You should also set PCI_RAM_ADDR_LENGTH and WB_RAM_ADDR_LENGTH to 4. You will need RAM16X1D.v simulation model from xilinx - if you have any of their synthesis tools available, you can find it in "install_dir"\verilog\src\unisims. You will also need glbl.v in "install_dir"\verilog\src ////////////////////////////////////////////////////////////////////////// I am using the Memec Saprtan II 2s200 board to implement the core. My question is: How or where I need to use the Xilinx "glbl.v" file? Also, in the pci rtl folder there is a file called "pci_ram_16x40.v" which is the one used in "pci_pci_tpram.v" and "pci_wb_tpram", but in this e-mail they refer to a "RAM16X1D.v", Do I need to change to the design to use "RAM16X1D.v" instead of "pci_ram_16x40.v"? Thank you for your help, Regards, Jorge |
|||
|
Xilinx "jlbl.v" file
by Unknown on Nov 21, 2005 |
Not available! | ||
|
The Xilinx glbl.v file just needs to be taken into account when you run your
simulations. For example, if you simulate using Icarus Verilog, you just
include the glbl.v file with your other Verilog design files (as well as the
Xilinx specific ones). It provides functionality that is used in the Xilinx
specific models (unisims stuff).
If you have defined PCI_XILINX_DIST_RAM pci_ram_16x40.v (which contains the
distributed RAM instances) is used for the implementation of
pci_pci_tpram.v. There isn't anything special to do here unless you need to
simulate the design. In Icarus, I just include the path to the Xilinx
simulation models with the -y option.
On 11/21/05, jtrabal at engin.umass.edu jtrabal at engin.umass.edu> wrote:
Hi,
I was reading the old pci forum e-mails and I found the following:
///////////////////////////////////////////////////////////////////////
Just to remind you, if you didn't do that already:
If you define PCI_XILINX_DIST_RAM and WB_XILINX_DIST_RAM,
you also have to define PCI_RAM_DONT_SHARE and
WB_RAM_DONT_SHARE, since
distributed RAM cannot be shared between two FIFOs - It only has one
write
and one read port.
You should also set PCI_RAM_ADDR_LENGTH and
WB_RAM_ADDR_LENGTH to 4.
You will need RAM16X1D.v simulation model from xilinx - if you have any
of
their synthesis tools available, you can find it in
"install_dir"\verilog\src\unisims.
You will also need glbl.v in "install_dir"\verilog\src
//////////////////////////////////////////////////////////////////////////
I am using the Memec Saprtan II 2s200 board to implement the core.
My question is: How or where I need to use the Xilinx "glbl.v" file? Also,
in the pci rtl folder there is a file called "pci_ram_16x40.v" which is
the
one used in "pci_pci_tpram.v" and "pci_wb_tpram", but in this e-mail
they refer to a "RAM16X1D.v", Do I need to change to the design to
use "RAM16X1D.v" instead of "pci_ram_16x40.v"?
Thank you for your help,
Regards,
Jorge
_______________________________________________
http://www.opencores.org/mailman/listinfo/pci
-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://www.opencores.org/forums.cgi/pci/attachments/20051121/24cc2fea/attachment.html
|
|||
1/1