Hello, pci_bridge_design_document.pdf mentions something about the file top.v but I cannot find this file and I think I need this file for an FPGA implementation. My problem is that I would like to have inout ports instead of separated in ports and out ports so I can connect those inout ports to the FPGA pins. According to the design document the file top.v would do that for me but this file is not there. Any help on that would be appreciated. Regards, Robert -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/pci/attachments/20051122/c52cf907/attachment.html

Robert Lluís Garcia wrote:

That is because it is *your* top-level design file. You have to provide it and wrap the PCI core and any other logic in your design in it. Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Hey Robert,

I understand the confusion, because on page 9 of the PCI IP Core Design
Document, it talks about editing the top.v file for ASIC implementation.
This statement makes it seem like there is a top.v that comes with the
core, but I believe its only part of the test-bench section. However,
this file is not provided because you need to create your own top.v to
implement the PCI IP Core to your hardware, which will allow you to
assign your I/O ports to your needs. This top.v file will not only
contain the PCI IP Core, but the buffer and ports to the PCI bus and any
other logic that will be connected to the Wishbone side of the core.
Think of the top.v file as your wrapper file.

I hope this helps,
Nick

Robert Lluís Garcia wrote:

-- ------------------------------------------------------------------------ Nicholas P. DiMonte Engineering Specialist Advanced Photon Source, ASD Argonne National Laboratory (630) 252-8856 npd at aps.anl.gov www.aps.anl.gov -------------- next part -------------- Skipped content of type multipart/related