Hi, I'm using the OpenCores PCI Bridge core to implement a PCI target unit and require the target to handle burst reads. My problem is that every Memory Read command (C/BE# = 0x6) results in the PCI bridge issuing a retry. In this case, how is the PCI master meant to keep FRAME# asserted over a number of clock cycles to indicate a burst read transaction? In the PCI Bridge's Core specification page 90 Figure 6.19, the timing diagram shows that FRAME# asserted over 5 clock cycles. I found the closest thing to a burst read of the target is to issue a Memory Read Multiple (C/BE# = 0xC) or Memory Read Line (C/BE# = 0xE). While this is a workaround, my issue with this is that my current design memory is not considered prefetchable. Cheers, -- Joseph Tan Hardware Engineer -------------------------------------------------- Tenix Defence Pty Ltd Electronic Systems Division Second Avenue, Technology Park Mawson Lakes, South Australia 5095 Email: joseph.tan at tenix.com Ph +61 08 8300 4418 (Australia) Fax +61 08 8349 7420

TAN Joseph wrote:

All PCI read requests are handled as Delayed READs by the PCI core. This means that all reads shall be terminated with retry whilst they complete on the wishbone bus. Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

I suggest using a core without any other interface, a native pci core will do. It will simplify the problem and will help you to achieve burst reads if needed. I made myself a core when i have that kind of problem. Cheers, Kerby Original Message: ----------------- From: TAN Joseph Joseph.TAN at Tenix.com Date: Fri, 2 Dec 2005 18:46:04 +1100 To: pci at opencores.org Subject: [pci] PCI read burst Hi, I'm using the OpenCores PCI Bridge core to implement a PCI target unit and require the target to handle burst reads. My problem is that every Memory Read command (C/BE# = 0x6) results in the PCI bridge issuing a retry. In this case, how is the PCI master meant to keep FRAME# asserted over a number of clock cycles to indicate a burst read transaction? In the PCI Bridge's Core specification page 90 Figure 6.19, the timing diagram shows that FRAME# asserted over 5 clock cycles. I found the closest thing to a burst read of the target is to issue a Memory Read Multiple (C/BE# = 0xC) or Memory Read Line (C/BE# = 0xE). While this is a workaround, my issue with this is that my current design memory is not considered prefetchable. Cheers, -- Joseph Tan Hardware Engineer -------------------------------------------------- Tenix Defence Pty Ltd Electronic Systems Division Second Avenue, Technology Park Mawson Lakes, South Australia 5095 Email: joseph.tan at tenix.com Ph +61 08 8300 4418 (Australia) Fax +61 08 8349 7420 _______________________________________________ http://www.opencores.org/mailman/listinfo/pci -------------------------------------------------------------------- mail2web - Check your email from the web at http://mail2web.com/ .