Hi, every PCI_IP users,
I've got a little configuration problem with a Master implementation
of the PCI IP:

I configure the Whisbone Image 2 as following
- WB_CONF_SPC_BAR : 0x00300000
- W_IMG_CTRL2 : 0x00000000 image without address translation,
without Prefetch and without Memory Read Line Enable
- W_BA2 : 0x00301000 as a memory space image
- W_AM2: 0xFFFFF000
- W_TA2: 0x00000000

These values are configured throught the Wishbone bus (they are not the
reset values)

I use an Altera FPGA and re-declare the memory block. I think it works
fine because configuration cycles are OK. Here is my configuration file
-----------------------------------------------------------------------------------------------------------------
`define WBW_ADDR_LENGTH 4
`define WBR_ADDR_LENGTH 4
`define PCIW_ADDR_LENGTH 4
`define PCIR_ADDR_LENGTH 4

`define FPGA
//`define XILINX
`define ALTERA

`define WB_RAM_DONT_SHARE
`define PCI_RAM_DONT_SHARE

`ifdef FPGA
`ifdef XILINX
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo
storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo
storage definition
`define PCI_XILINX_RAMB4
`define WB_XILINX_RAMB4
//`define PCI_XILINX_DIST_RAM
//`define WB_XILINX_DIST_RAM
`else
`ifdef ALTERA
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit
fifo storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit
fifo storage definition
`define PCI_ALTERA_M4KRAM
`define WB_ALTERA_M4KRAM
`endif
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 3 // PCI target unit fifo
storage definition when RAM sharing is used ( both pcir and pciw fifo
use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo
storage definition when RAM sharing is used ( both wbr and wbw fifo use
same instance of RAM )
// `define WB_ARTISAN_SDP
// `define PCI_ARTISAN_SDP
// `define PCI_VS_STP
// `define WB_VS_STP
`endif

//`define ACTIVE_LOW_OE
`define ACTIVE_HIGH_OE

`define HOST
//`define GUEST

// `define NO_CNF_IMAGE
`define PCI_NUM_OF_DEC_ADDR_LINES 20

`ifdef HOST
`ifdef NO_CNF_IMAGE
`define PCI_IMAGE0
`endif
`endif

`define PCI_IMAGE2
//`define PCI_IMAGE3
//`define PCI_IMAGE4
//`define PCI_IMAGE5


`define PCI_AM0 24'hffff_f0
`define PCI_AM1 24'hffff_ff
`define PCI_AM2 24'hffff_f0
`define PCI_AM3 24'hffff_f0
`define PCI_AM4 24'hffff_f0
`define PCI_AM5 24'hffff_f0

`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used
as general PCI-WB image!
`define PCI_BA1_MEM_IO 1'b1
`define PCI_BA2_MEM_IO 1'b0
`define PCI_BA3_MEM_IO 1'b1
`define PCI_BA4_MEM_IO 1'b0
`define PCI_BA5_MEM_IO 1'b0

`define PCI_TA0 24'h0000_0
`define PCI_TA1 24'h0000_0
`define PCI_TA2 24'h0000_0
`define PCI_TA3 24'h0000_0
`define PCI_TA4 24'h0000_0
`define PCI_TA5 24'h0000_0

`define PCI_AT_EN0 1'b0
`define PCI_AT_EN1 1'b0
`define PCI_AT_EN2 1'b0
`define PCI_AT_EN3 1'b0
`define PCI_AT_EN4 1'b0
`define PCI_AT_EN5 1'b0

`define WB_NUM_OF_DEC_ADDR_LINES 20

`define WB_IMAGE2
// `define WB_IMAGE3
// `define WB_IMAGE4
//`define WB_IMAGE5
`define WB_BA1 20'h0040_0
`define WB_BA2 20'h0000_0
`define WB_BA3 20'h0041_0
`define WB_BA4 20'h0042_0
`define WB_BA5 20'h0043_0 // to be sure !!! ;-)

`define WB_BA1_MEM_IO 1'b1
`define WB_BA2_MEM_IO 1'b0
`define WB_BA3_MEM_IO 1'b1
`define WB_BA4_MEM_IO 1'b0
`define WB_BA5_MEM_IO 1'b0

`define WB_AM1 20'hFF00_0
`define WB_AM2 20'hFF00_0
`define WB_AM3 20'hFF00_0
`define WB_AM4 20'hFF00_0
`define WB_AM5 20'h0000_0

// initial value for WB translation addresses. The initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images
// are transleted to this adresses whithout access to pci_ta registers.
`define WB_TA1 20'h0000_0
`define WB_TA2 20'h0000_0
`define WB_TA3 20'h0000_0
`define WB_TA4 20'h0000_0
`define WB_TA5 20'h0000_0

`define WB_AT_EN1 1'b0
`define WB_AT_EN2 1'b0
`define WB_AT_EN3 1'b0
`define WB_AT_EN4 1'b0
`define WB_AT_EN5 1'b0

//`define ADDR_TRAN_IMPL

//`define WB_DECODE_FAST
// `define WB_DECODE_MEDIUM
`define WB_DECODE_SLOW

`define WB_CONFIGURATION_BASE 20'h00300

`define REGISTER_WBS_OUTPUTS

`define PCI33

-----------------------------------------------------------------------------------------------------------------

I enable the Master by writting a 0x7 value at address 0x00300004
but after that, when I would like to perform a write at e.g. 0x00301070
with the Sel_i value as "1111" and say, 0xA110B0B0
for the data. I can read on the PCI bus (in simulation) this following
sequence:

C_nBe __/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯\__
\ ___________0011___________/

Ad __/¯¯¯¯¯¯¯¯¯¯¯¯¯\/¯¯¯¯¯¯¯¯¯¯¯¯\___
\__0x00301002_/\_0x00301000_/

I don't understand why the command value is "0011" (I/O Write instead
of Mem Write), and why the first address is translated?
Finally where is the data?

For the last question, it is possible that the device does not response,
because the space is a memory space and the command
for the cycle is an I/O one.

Could anybody help me.

Thanks a lot for your time and answer.

Gilles