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flushing of un-read data
by Unknown on Apr 24, 2007
Not available!
Hi,

The PCI IP Core Spec (Rev 1.2) mentions that 'any data not read
from the PCIR_FIFO is flushed immediately after the read
transaction is finished...' (pg. 34).

We have a data FIFO that will be read as a target over PCI. Each
read leads to a pop of the data FIFO. If the PCIR_FIFO has
prefetched data from the data fifo and get flushed, this data is lost.
The FIFO state changes on each pop so there's no way to recover
the lost data.

A couple of questions:
1) Is there a mode where the prefetched data is not flushed on
completion of the PCI transaction? Some commercial cores seem to
support such a mode for FIFO-like applications.

2) Does the core indicate how many prefetched words were
flushed? Given this information, it might be possible to implement a
rollback mechanism externally.

Thanks,
Prashant Arora
flushing of un-read data
by Unknown on Apr 24, 2007
Not available!
Hi, see below, Regards, Miha Dolenc ----- Original Message ----- From: arora.pra at gmail.com> To: pci at opencores.org> Sent: Tuesday, April 24, 2007 4:11 AM Subject: [pci] flushing of un-read data
Hi,

The PCI IP Core Spec (Rev 1.2) mentions that 'any data not read
from the PCIR_FIFO is flushed immediately after the read
transaction is finished...' (pg. 34).

We have a data FIFO that will be read as a target over PCI. Each
read leads to a pop of the data FIFO. If the PCIR_FIFO has
prefetched data from the data fifo and get flushed, this data is lost.
The FIFO state changes on each pop so there's no way to recover
the lost data.

A couple of questions:
1) Is there a mode where the prefetched data is not flushed on
completion of the PCI transaction? Some commercial cores seem to
support such a mode for FIFO-like applications.

Prefetchable address space means that reads don't have side effects,
which is not the case with FIFOs.

2) Does the core indicate how many prefetched words were
flushed? Given this information, it might be possible to implement a
rollback mechanism externally.

No such mechanism is implemented.

You could play arround with small RAM in front of FIFO acting
as "rollback" buffer or capturing last address of previous transfer
comparing it to first address of new transfer to determine how
many words were flushed. Just my two cents on the issue.

Thanks, Prashant Arora _______________________________________________ http://www.opencores.org/mailman/listinfo/pci


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