I'm looking for a behavioral/simple structural PCI verification core to drive the bus along with the "real" PCI core. I did a search on the archives but I don't see anything matching that. Does anyone have any ideas? Thanks! J. Michael Lodman Solekai Systems Corporation 3398 Carmel Mountain Road San Diego, CA 92121 USA mlodman at solekai.com Tel: 858.436.8419 Fax: 858.436.2041 Cell: 760.271.4347 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/pci/attachments/20070613/49199cc0/attachment.html

On 13 Jun Lodman, Mike wrote:

One of the OpenCores PCI implementations (I think it's called pci_core) includes a VHDL behavioural model PCI master driven by a text file - using this you can generate most PCI accesses in a testbench. HTH, -- Christian Ludlam christian at recoil.org