HI!!
me new user to verilog....

How the file inclusion ( `include ) compiler directive is used to insert the
entire contents of a source file in another file during compilation.i.e. The
result is the contents of the included source file appear in place of the
`include compiler directive.IS the `include compiler directive can be
used to include global or commonly used definitions and tasks without
encapsulating repeated code within module boundaries.
suppose i wrote one file name "pci_user_constants.v" ... and this file to
be included in "pci_constants.v"as

`include "pci_user_constants.v"

but while checking syntex in Xilinx it shows error like such file does not
exist...
how can i include such file



some body from net replied me this way


In the Xilinx project manager, go the menu: Process -> Properties

Then do this:
1) Click the category 'Synthesis Options'
2) Now, near the bottom-right of the window, change
'Property display level' -> Advanced

3) Inside the 'Property Name' scroll-box,
look for table-entry "Verilog Include Directories"
Change this to the correct path (i.e. location of your `include files)

I Gone through the steps ....

1)Right Click on 'Synthesis Options' then i entered to properties
2) Now, near the bottom-right of the window, change
'Property display level' -> Advanced

3) Inside the 'Property Name' scroll-box,
look for table-entry "Verilog Include Directories"
Change this to the correct path (i.e. location of your `include files)
which file to be included there i m gating
1)_projnav
2)_xmags
3)xst->work->vlg3c......

i tried all the way but still it shows an error
Could not find include file 'file name.v'