Hi, I am trying to get the pci_bridge32 to be recognized by my motherboard. I have used the Altera PCI IP Core on the board and it works fine so I know it is not a board issue. When using pci_bridge32 it does not show up in the "PCI devices list" on boot up. You can see my top level at http://www.cetoncorp.com/pci_wb_test.v I have stubbed out the wb interfaces, I am never doing an interrupt and use bufif0 for tri-stating. If someone could take a look and see if something pops out at them I would greatly appreciate it! Also, I am using the default (currently in CVS) pci_user_constants.v One other thing. I need to make one 32k memory bar. The pci_user_constants are a little confusing to me. Bars on the PCI side are images correct? So if I comment out PCI_IMAGE2-5 I should have PCI_IMAGE0 (config space) and PCI_IMAGE1 (the first bar) created for me right? To make it a memory space instead of IO I need to make PCI_BA1_MEM_IO 1'b0. And to make it 32k I need to make PCI_NUM_OF_DEC_ADDR_LINES 17. I have ADDR_TRAN_IMPL commented out right now so the address translation stuff shouldn't matter I think. I just want to make sure I am understanding this correctly since I can't seem to get it working to check my assumptions. Thanks! -Jeremy

Hi, your assumptions regarding PCI BARs' configuration are correct. I've taken a look at the top level, it seems allright. I suggest changing "bufif0" instances with generic code (you know en ? 1'bz : data). Have you selected PCI I/O standard for your top level signals? Best regards, Miha Dolenc ----- Original Message ----- From: "Jeremy Hammer" jeremyh at cetoncorp.com> To: pci at opencores.org> Sent: Monday, July 30, 2007 6:32 PM Subject: [pci] pci_bridge32 on an Altera Cyclone II

Hi Miha, I have put a new top level at http://www.cetoncorp.com/pci_wb_test.v There is now a define at the top of the file called USE_WB which switches between pci_bridge32 and the altera PCI core. If I leave the define commented out (using altera's pci core) it works fine, if I leave it in (using pci_bridge32) it does not work. I did this to verify the IO signals are correct on the project. In this file there are some extra signals (pme and m66en) which are for my board. Also, idsel is ad[24] on my board so it is commented out in the input listing. Again, this works with altera's so I know the project and these signals are correct. I changed bufif0 to en ? 1'bz : data and it did not change anything. I'm not sure what to do now. Do you happen to have a very simple top level you know works in other systems I could try? I saw one in the source but it had tons of rams and was specific to Xilinx. Thanks for your help, -Jeremy Miha Dolenc wrote:

Jeremy Hammer wrote:

Can you post your pci_user_constants.v file? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

It is the default (in CVS) file. It is at http://www.cetoncorp.com/pci_user_constants.v for easy access though. -Jeremy Mark McDougall wrote:

Hi,

I am going through the compile output and these lines are particularly
concerning to me.

Info: Pin pci_framen has a permanently disabled output enable
Info: Pin pci_irdyn has a permanently disabled output enable

Info: Pin pci_framen has VCC driving its datain port

I am following the signals to their origin and they seem to be fine,
although it gets difficult to tell when you go in deep.

Also, I put the PCI I/O assignments on and it didn't help. And yes I
found the correct way to assign the PCI I/O assignments to the pins.

What are your thoughts on the three "Info" lines from my compile?

Thanks!
-Jeremy

Jeremy Hammer wrote:



If you are never mastering the bus, then these lines will never be driven by the PCI core. So that's no problem. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Jeremy Hammer wrote:

Your header looks fine to me. (BTW your BAR1 is I/O space). You should at least get configuration space accesses as there shouldn't be anything in the user_constants file that can affect that for GUEST implementation. So I'm at a loss to explain your problem. :( The only other thing I can suggest is to rip out the arbiter from the pci testbench and build a testbench to simulate your design. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Hi Jeremy! Infos look OK to me, as you have WISHBONE Slave interface's control signals tied off to zero, so PCI Master won't ever do any accesses and PCI Target never drives FRAME or IRDY. I'm puzzled why this doesn't work for you! I have only one idea left (it's a long shot though :)): Can it be, that device isn't shown at boot-up because BIOS doesn't recognize the vendor ID? Can you change it to the Altera's core one and try that? The only other course of action I can recommend from here on is simulation - just read vendor/device ID and configure BAR's. Then if this works, work through gate level and timing simulations - if it's not board problem, the thing should break at some point. Is there anyone on the list using the core in Altera to help us out? I know that at least a few people have used the core succesfully on Altera. Best regards, Miha Dolenc ----- Original Message ----- From: "Jeremy Hammer" jeremyh at cetoncorp.com> To: "Discussion list about free, open source PCI IP core" pci at opencores.org> Sent: Friday, August 03, 2007 7:56 PM Subject: Re: [pci] pci_bridge32 on an Altera Cyclone II

Hi Jeremy, I been using the pci_bridge32 core in an Altera PCI dev-card (Cyclone II EP2C35F672C6 based FPGA), the BIOS successfully recognizes the board, I/O and memory and configures the BAR's, everything looks ok so far. I'm using an efika (PPC based board, http://www.efika.de/index_en.html) and successfully manage to compile the test programs in /apps/test/rtl/verilog/* using Gentoo and Jungo drivers evaluation copy. some tweaking required in clocks1_top_test.v RAMB4_S16_S16.v is required if you define in pci_user_constants.v `define PCI_XILINX_RAMB4 `define WB_XILINX_RAMB4 ...... `define PCI66 `define HEADER_DEVICE_ID 16'h0004 `define HEADER_REVISION_ID 8'h01 `define HEADER_VENDOR_ID 16'h1172 `define WB_RTY_CNT_MAX 8'hFF `define PCI_WB_REV_B3 `define PCI_WBS_B3_RTY_DISABLE `define PCI_MBIST_CTRL_WIDTH 3 `define WB_CONFIGURATION_BASE 12'h00_0 `define HEADER_SUBSYS_VENDOR_ID 16'h0000 `define HEADER_SUBSYS_ID 16'h0000 `define HEADER_MAX_LAT 8'h00 `define HEADER_MIN_GNT 8'h00 make an RAMB4_S16_S16.v with quartus mega Wizard (altsyncram function) that looks like: module RAMB4_S16_S16 ( data_a, wren_a, address_a, data_b, address_b, wren_b, clock_a, enable_a, clock_b, enable_b, aclr_a, aclr_b, q_a, q_b); input [15:0] data_a; input wren_a; input [7:0] address_a; input [15:0] data_b; input [7:0] address_b; input wren_b; input clock_a; input enable_a; input clock_b; input enable_b; input aclr_a; input aclr_b; output [15:0] q_a; output [15:0] q_b; wire [15:0] sub_wire0; wire [15:0] sub_wire1; wire [15:0] q_a = sub_wire0[15:0]; wire [15:0] q_b = sub_wire1[15:0]; altsyncram altsyncram_component ( .clocken0 (enable_a), .clocken1 (enable_b), .wren_a (wren_a), .clock0 (clock_a), .wren_b (wren_b), .clock1 (clock_b), .address_a (address_a), .address_b (address_b), .data_a (data_a), .data_b (data_b), .q_a (sub_wire0), .q_b (sub_wire1), .aclr0 (1'b0), .aclr1 (1'b0), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), .rden_b (1'b1)); defparam ...... endmodule still, you should be able to get the card recognized, even with the //`define PCI_XILINX_RAMB4 //`define WB_XILINX_RAMB4 (commented) finally, the pin assignment is important, according to the board. which dev-board are you using. I miss the Cyclone II FPGA spec. regards, Joel Rodriguez ODM Technologies Mira Mesa, CA P.S. Miha thanks for such a wonderful core :). Miha Dolenc wrote:

Miha Dolenc wrote:



No, the BIOS doesn't "recognize" _any_ vendor IDs at all.

We have used it successfully in Altera devices (EP2C20/35). Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Hi Everyone,

Thank you for all your help and suggestions. Unfortunately I am out of
town right now and cannot try any of them yet. This is on an EP2C35. I
should be back at the end of this week to test it.

Again, thanks for all the help!
-Jeremy

Any update on this? I have a project that is experiencing very similar issues.

I've compared my top level against the test application and it seems to be very similar (my pin names are different). I've also triple-checked the pinout and that seems OK too.

Attached is the user constant file.

Just an update. I was never able to get the BIOS to see this device. But just as a lark I decided to let it boot through to linux and see if linux could tell me anything. And there was my device!

So I've moved past this point.

BTW, the user constants have changed quite a lot so don't use what I posted before as a basis for anything.

James.