Hey All, Firstly a bit about my background. I am currently at university and have extended experience with 8 and 16 bit microcontroller and analog circuits however I don't know much if anything (apart from the basic course I undertook) about digital logic design about FPGA so I wanted to undertake a few projects to change this. What I want to accomplish is to build a device which can sample data at a very high rate say 1GSa/s, buffer it to ram (if necessary) and convey it to my computer for analysis via the PCI bus. I know I'm definately diving into the deep end with this but I'm sure I can pull it off with some advice from people in the know. Ok finally my questions. I have been reading up about PCI and from an application perspective what exactly is the difference between a PCI target, PCI master and PCI bridge? For example since I will be putting the PCI card into my computer I will need a PCI target am I correct? I am assuming that my PC will be a master and you cannot have two masters or can you? Secondly with regard accessing the PCI card from application software on the PC side do I need to write special PCI drivers or do I use generic drivers that are availible on a windows xp machine? Also does anyone know where I can get the spec for PCI, I have looked but it appears you have to purchase it from PCI SIG and since this is an educational project I don't really have the necessary funding for it, pretty much spending every penny to make the hardware. I am also trying to get hold of a copy of PCI system Architecture by Tom Shanley and Don Anderson - 3rd edition but my local bookstore said the publisher is out of stock at it will take a few weeks. Again for the timebeing anyone know of ebook versions of the book that may be available? Finally would you recommend any other literature that I should familiarise my self with? Thanking you in anticipation! Greg __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/pci/attachments/20071025/d932bd2a/attachment.html

G.Franco wrote:



Just be aware that absolute maximum 32-bit PCI33 rate is around 120MB/s,
and more likely 80-100MB/s sustained rate with nothing else on the bus.



A PCI Master can initiate PCI transactions. eg. PCI mobo, or bus-mastering
card like DMA.
A PCI target can only respond to Master transactions. eg. data acquisition
card without DMA.
A PCI Bridge connects a PCI bus to another PCI or non-PCI bus. Technically
the opencores PCI bridge is exactly that - it bridges the PCI bus and the
Wishbone bus.

You'll need to implement a target at least - or master if you want a DMA
engine on your card. The opencores PCI bridge is suitable for both purposes.

There can be many PCI masters on a bus - one arbiter which is responsible
for granting access to masters that request the bus. Generally the arbiter
is on a PC mobo.

As for drivers, depends on how you implement your device. It is possible
to use generic drivers (like TVICPCI) that allow you to map device
resources into (Windows) user-space. I'm sure there's similar under linux,
though writing a kernel driver module is a lot easier than windows.

Good choice! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Thanks Mark. I have had a chance to find some more information since I posted that message and have some followup questions. I read some of the datasheets for the bridge and was unclear about what is ment by Image. There are references to you can have several images. Also at this point would you suggest I continue research into PCI or would looking at PCI express be a better option? In some of the previous posts this months there has been discussion about xilinx having devices with hardcores for pci express, is this something like a peripheral unit eg. adc on a microcontroller if I can use that analogy, which I simply read and write to or is it just a permanently wired up IP core to which connections are made ie It has some preset parameters and is not as configurable. Correct me if I am wrong anywhere here but from what I have understood the Bridge IP core should allow me to do the following. I have my own PCI card that I put into a PC. On the PC side I have an application written in C# for example the role of which is to process the sampled data and graphically display it for the user. Once the application is started up it sends commands to the PCI card (card is now a target) the card inteprets the information and begins its data acquision. The acquired data is written to onboard DDR(2) SDRAM. Now this is where I am a bit unclear. Do I need to make an interrupt request to the host PC to get access to the bus or do I wait for there to be no traffic? (or is this handled by the bridge?) Once able to transmitt data I setup a DMA engine to shift the massive amount of sampled data to the host. Can you explain how the data is handled when it reaches the host? I'm completely new to the PCI interaction with the software side so this is a grey area at the moment. My application on the host accesses the data and processes it before generating images to display the data. Also the 100MB/s is not a major hassel since I will only be sampling for short periods and storing to ram I intend to have on the board, before sending it across to the PC. Regards, Greg ----- Original Message ----- From: Mark McDougallmarkm at v...> To: Date: Fri Oct 26 01:38:46 CEST 2007 Subject: [pci] Rookie questions about PCI

make_u_play at yahoo.com wrote:

An image is a contiguous block or window of memory or I/O space - see BAR
in PCI documentation.



I'm not overly familiar with Xilinx PCIe offerings, or indeed PCIe itself,
though I have done some research into it for a customer. A hard-core is a
fixed functional block, but it should still be quite configurable. I
suspect for your purposes, functionally a hardcore would be perfectly
adequate.

Whether PCI or PCIe is the way to go would depend on what your
requirements are. If your card won't be produced commercially, and you
have lower bandwidth requirements, personally I'd stick with PCI. Why? You
don't have to worry about gigabit transmission on your PCB, and I suspect
that PCI is easier to debug on both a hardware and software level.

BTW are you producing your own board? Or are you going to use a PCI/PCIe
FPGA evaluation board for this?



That's certainly feasible, yes! I know nothing about C# but I assume you'd
need some sort of driver - even if generic - to talk to your card. You'd
do so by reading/writing registers mapped by your card into memory or I/O
space.



Bus arbitration is handled transparently by the arbiter on the PC host and
the PCI core in your card - you simply need to request a transfer (eg.
memory read/write request to PCI space mapped by your card) and it'll
happen once the bus is available.



Yes, but now you're mastering so your core would have to have that
capability (which opencores PCI does).



Typically your application would have a user-mode buffer into which data
is read from your card by the application. Without DMA, you'd simply be
reading from memory or I/O space mapped by your card and writing to your
application buffer. With DMA, you'd supply the physical address of the
application buffer to the DMA engine - whose registers are also mapped
into memory or I/O space on your card - and then tell it to start
transferring. Once the DMA is finished, you could get a PCI interrupt, or
you could poll a status register in the DMA engine.

BTW there is also an opencores DMA engine.

So PCI should suffice then. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Thanks heeps all this info is really helpful!



Initially I am planning on getting a generic board with a PCI connector
and using it but I plan on designing my own board using Altium designer
once I have a working prototype. I know a few people that will probably
chip in so I can spread the cost of having a board made + I know a
place in china that will make a board with the following spec for about
$700 setup + $120 a board (1 - 10 boards) and I was planning on
getting Dayang to mount all the BGA and QFN packages for me.
Layers 10
Board Size (width) 200 mm
Board Size (height) 120 mm
Min. Tracing/Spacing 0.07 mm
Min. Annular Ring 0.10 mm
Smallest Holes 0.10 mm

Ok I was having a look at http://www.fpga4fun.com/PCI2.html. It says "The disadvantage of the IO space is that it's small (limited to 64KBs on PCs, even if PCI supports 4GBs) and pretty crowded. " I also had a look at the I/O space addresses on my PC and it is crowded and limited to a max address of xxxxx....FFFF. Can you explain the difference between I/O space and memory space from a hardware and software point of view. Basically what I want to know is from the computers perspective what is so different between I/O space and memory space? From what I can see they are pretty much the same sort of thing i.e. I access both by an address and read or write data to both. What are the unique aspects of each that make them special and different? With regard to the BAR I do recall having read about it a few years ago. I will search through the documentation with that in mind as soon as I get a copy. But to clarify the base address register is the register(s) in the config space that is updated by the host pc telling the card where the assigned memory space has been mapped to correct? Also how does the card know how much memory space has been assigned to it? Now say infact that I wanted to have 4GB of RAM on my PCI card. I choose 4GB since its well over the direct addressing limit for a 32 bit system. So if I want to access all of the 4GB in which there is data how will I go about this? There is a limit to how much memory space I can be assigned am I correct? and beyond this I will have to impliment some type of indirect addressing or paging scheme where I tell my PCI card to switch between two 2GB ram sections? What exactly is a user-mode buffer? Also by application buffer do you just mean an array in my program and nothing special right? When you say the DMA's registers are mapped to memory or I/O space that is simply so I can update the destination address for the transfer right? (The only DMA I have delt with is on an MSP430 microcontroller where you supply a source address, dest address and #bytes or words + trigger source etc... and it finishes the transaction and calls an interrupt is it exactly the same thing with a PC?) Many thanks, Greg ----- Original Message ----- From: Mark McDougallmarkm at v...> To: Date: Fri Oct 26 05:41:23 CEST 2007 Subject: [pci] Rookie questions about PCI

make_u_play at yahoo.com wrote:


and IO space. IO space has more limitations as well, such as not being
prefetchable. I think the legacy of IO space was to reduce the decode
logic required by IO peripherals, and perhaps optimise IO performace in
the CPU?!?

These days, just use PCI memory space.



Yes. In the case of the opencores PCI controller, you set the size of each
memory or IO space image in a header file before you build the FPGA. The
PC BIOS must assign a memory range that is the requested size. The way
it's actually done is the BIOS writes 1's to the BAR and reads it back -
the unimplemented low-order bits determine the size of the image.



You won't get anywhere *near* 2GB successfully assigned to your card, and
nor should you attempt it. You'll have to choose something a *lot*
smaller, and implement a bank-switch register in your device. Note that if
you're using a DMA engine on your card, then it's likely you won't need to
make the memory space visible at all to the PCI (though you probably
should implement a small window, even for debug).

Yes. A user-mode buffer is a buffer that you can access from a normal application. If you're doing DMA, you'll need some mechanism to allocate or find the *physical* address of such a buffer. Here's where you might need a generic driver like TVPICPCI. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266