Hi, I have a Nallatech BenNuey-PCI-4e FPGA. The board features 2 Xilinx FPGAs. A Spartan-II with pre-configured firmware to control the 64-bit/33Mhz PCI interface and a Virtex-II Pro for user application. The Spartan device which handles the PCI interface has the following interface signals: EMPTY (O) Indicates if Spartan has data to transmit BUSY (O) Indicates if Spartan can receive data AS/DS# (O) Determines if data input is address or data RST# (O) System reset RD#/WR (I) Indicates if interface is writing/reading Spartan REN#/WEN# (I) Enables read/write operation INT# (I) Interrupt signal ADIO (I/O) 32-bit data bus CLK (I) Internal clock RESET (I) Reset internal Signals I would like some advice on how to do VHDL programming model on this. My goal is to upload the FPGA with a data intensive algorithm that constantly checks an input file for data and writes out a text file whenever there is an output data available. I have ISE 9.1 Foundation to work with but i dont have the PCI Core Generator License. Please advise. Sincerely, Justin ___________________________________________________________ Want ideas for reducing your carbon footprint? Visit Yahoo! For Good http://uk.promotions.yahoo.com/forgood/environment.html -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/pci/attachments/20071120/af83b7a5/attachment.htm