Hi, i'm doing some tests on the pci bridge compiled as host (I compile
the project with Icarus Verilog)

Inside "task test_wb_image", after this lines:

1560 // prepare base address register
1561 config_write( ba_offset, image_base, 4'hF, ok ) ;

I have added these other lines:

1562 config_read( ba_offset, 4'hF, my_reg) ;
1563 $display(" my_reg=%h, image_base=%h, wb_base_addr1=%h ", my_reg,
image_base, bridge32_top.bridge.configuration.wb_base_addr1);

but during the simulation, the last command shows that the three
values are different:



Should the three values be equal?
If so, Is this a bug occoured in the compilation/simulation?

thnks in advance,
Paolo