forwarded to correct list...



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Hi Howard, regarding the drivers - you can try uploading them into the CVS yourself into some meaningful :) directory. Otherwise you can send them to me and I'll try (it has been a while since my last update). Regarding read latency: All reads are handled as delayed which increases latency. This is done to meet PCI specifications' target initial latency requirements in all possible cases. It is a bridge core which does not have any knowledge about the backend design, so there is no other way to do it. Another problem, as Mark pointed out, are PC motherboards or better yet, their chipsets. It depends how they handle retries and in most cases won't perform read/write bursts. You can try and play around with MTRR settings (assuming x86 platform) - I've enabled bursts of 2 (VIA chipset) and 4 (Intel chipset) with those (not worth the effort though, as FIFOs are never prefetchable). If the latency is killing your application, the only way out with this core (and any other too, if you ask me, judging by conversations on PCI-SIG mailing list) is bus mastering (DMA). The core has its share of drawbacks on this side too, but should suffice for transfers to system memory (writing). Anyhow, if you need professional support, commercial license, customization of the core or anything alike and have a budget set aside for it :), you can visit www.beyondsemi.com for more information. Best regards, Miha Dolenc ----- Original Message ----- From: Howard Harte To: pci at opencores.org Sent: Sunday, February 17, 2008 3:33 AM Subject: [pci] PCI core read latency question forwarded to correct list... From: Howard Harte opencores at dublintrees.com> Date: February 16, 2008 5:00:22 PM PST To: "cores at opencores.org" cores at opencores.org> Subject: PCI core question I'm using the OpenCores PCI core in a Spartan3 FPGA. It works very well, and I haven't run into any compatibility issues with any of the PC's I've tried it with, and I wrote drivers for it for Windows XP (using KMDF) and Linux. I'd be happy to contribute those to OpenCores if there is interest. One issue I'd like some advice on is improving read latency. For single 32-bit writes, they complete in about 300ns, which is fine. For 32-bit reads, they complete in 2.5uS, which is a really long time. I'm reading and writing to a FIFO, which occupies a single address on the wishbone backplane. Some things I've thought about are mapping the FIFO to a separate BAR, ignoring the lower address bits, and enabling read prefetching, but figured this might be dangerous since it's a FIFO. Another thing I considered is doing bus mastering to empty the FIFO into main memory, but this is a large change to my design. Any other thoughts on how to proceed? I tried the pci32tlite core, and it worked ok in some systems, but I ran into compatibility issues on a Dell Optiplex 700mhz P3 system so I switched over to the larger OC PCI core. In my design, the wishbone and PCI are operating from the 33MHz PCI clock. Thanks, -Howard _______________________________________________ http://www.opencores.org/mailman/listinfo/pci