1/1 
|
STOP#
by hmee907 on Nov 4, 2008 |
hmee907
Posts: 2 Joined: Jun 5, 2008 Last seen: Oct 18, 2018 |
||
|
Is there any way to specify PCI wait states?
The following is for single PCI transfers: When I perform a write, the TRDY# signal gets asserted fairly quickly. Before the data is out of the Wishbone FIFO. When I perform a read, the PCI bus doesn't get a response back until the fourth PCI access cycle. The first 3 get the STOP#. The system is configured for the Guest Mode, 33MHz, and I'm using BAR1 to access the board. Thanks for any feedback on this |
|||
|
STOP#
by Unknown on Nov 4, 2008 |
Not available! | ||
|
hmee907 at hotmail.com wrote:
When I perform a write, the TRDY# signal gets asserted fairly quickly.
Before the data is out of the Wishbone FIFO. Writes are posted.
When I perform a read, the PCI bus doesn't get a response back until
Yup, the performance of the core is pretty ordinary for reads. The core
will automatically post the read and disconnect immediately. If you want
near-bus speeds, you'll need to add a DMA engine to your device and do
bus-mastering DMA.
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
the fourth PCI access cycle. The first 3 get the STOP#. |
|||
|
STOP#
by Unknown on Nov 4, 2008 |
Not available! | ||
|
Can any one of you mentor me in my robotic semester proejct or refer me to
someone
Thanks in advance
On 11/4/08, hmee907 at hotmail.com hmee907 at hotmail.com> wrote:
Is there any way to specify PCI wait states? The following is for single PCI transfers: When I perform a write, the TRDY# signal gets asserted fairly quickly. Before the data is out of the Wishbone FIFO. When I perform a read, the PCI bus doesn't get a response back until the fourth PCI access cycle. The first 3 get the STOP#. |
|||
|
STOP#
by hmee907 on Nov 5, 2008 |
hmee907
Posts: 2 Joined: Jun 5, 2008 Last seen: Oct 18, 2018 |
||
|
----- Original Message -----
From: Mark McDougallmarkm at v...>
To:
Date: Tue Nov 4 08:10:52 CET 2008
Subject: [pci] STOP#
hmee907 at hotmail.com wrote:
> When I perform a write, the TRDY# signal gets asserted fairly
quickly.
> Before the data is out of the Wishbone FIFO.
Writes are posted.
> When I perform a read, the PCI bus doesn't get a response back
until
> the fourth PCI access cycle. The first 3 get the STOP#.
Yup, the performance of the core is pretty ordinary for reads. The
core
will automatically post the read and disconnect immediately. If you
want
near-bus speeds, you'll need to add a DMA engine to your device and
do
bus-mastering DMA.
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Ok, thanks for the feedback.
|
|||
1/1