Hello,

Does anyone have a good resource that explains the address translation of the pci_bridge32 module? Both translation from PCI to Wishbone and vice-versa?

I can read and write via PCI and see (with SignalTap) various FIFO's being enabled that make sense. But nothing ever gets to the wishbone side (again viewing with SignalTap). So I'm guessing that I don't have the translation setup correctly and the core is throwing away the accesses because they don't match the address after the translation.

Cheers,

James.

Hello,

I'm having the same problem. Did you find a solution?

I had same problem, it did not work (PCI > WB). I wanted to use translated part as bar hit indication.
The problem was mainly in the fact that Verilog is not strong typed and allows such misleading mistakes in the code. I have never used Verilog before and it took some time and my coworkers eyes to spot the problem.

Check the file pci_user_constants.v where there are constants:

// initial value for PCI translation addresses. The initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images
// are transleted to this adresses whithout access to pci_ta registers.
`define PCI_TA0 24'h0000_0
`define PCI_TA1 24'h0000_0
`define PCI_TA2 24'h0000_0

Vectors are 24 bit, but preset value is actually 20 bit (5 nibbles). This means that if you change the setting like this:
`define PCI_TA0 24'h4000_0

it will actually be h0400_00 because only 20 bits are provided and Verilog will fill leftmost nibble with zeros.

So you have to write it like this:
`define PCI_TA0 24'h4000_00

I hope this helps.

Thanks for your answer!
It seems like I don't really get the address translation and hit genertion part.
If I have PCI_IMAGE0 defined and the base address of this image is 0x4000000.
How do I have to configure the pci core, so data which is written to this address,
is passed on to the wishbone bus? I'm pretty 'wandering in the dark'...

Thank you for your answer!
But it seems like I don't really get the hit generation.
How do I have to configure the bridge to write to the fpga?
E.g.
Image 2 is defined
`define PCI_IMAGE2
it is given the base address 0x40000000.

Then if a write transaction is on the bus with this address,
how is a hit gernerated, so that the data is passed on to the
wishbone-bus?