Hi
i want to change the code in pci_ram_16x40d in pci_bridge32 project that used xilinx RAM16X1D ram style.


here is my code

module pci_ram_16x40d (data_out, we, data_in, read_address, write_address, wclk);
parameter addr_width = 4 ;
output [39:0] data_out;
input we, wclk;
input [39:0] data_in;
input [addr_width - 1:0] write_address, read_address;

wire [3:0] waddr = write_address ;
wire [3:0] raddr = read_address ;

reg [39:0] my_memory [0:16];


always@(posedge wclk)
if (we==1'b1)
my_memory[write_address]

reg [39:0] myoutdata;
always@(posedge wclk)
myoutdata
assign data_out= myoutdata;
endmodule


I want to know am i doing the rith way or am i missing something. I'm newbie in verilog.

thanks in advance.