hi everyone, I have some questions about the PCI_Wishbon bridge IP core.

I want to realize a VME-to-PCI bridge using your design. And now I am in the stage of studying the characteristic of the bridge.

I modified a little in the pci_user_configration.v file, and realized a pci host in the design. When I access the wishbone slave port using a wishbone master behaviour module, most config-regs returded the value "0", and some return the value with some "x" bits. I can't even read the vendor ID or device ID. I commented the wishbone_b3 option in this situation.

Can anyone explain why this happened, and give me some advice?

I have the vsim.wlf file for you, which is generated in modelsim 6.3f. In the testcase I first write the first 0x400 configuration addresses with "0xaa5555aa", and after that I read them.

And I also pasted the pci_user_configration.v, please check it for me.