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PCIe Testbench from Altera
by prabul on Jun 14, 2010 |
prabul
Posts: 1 Joined: Jun 22, 2009 Last seen: Sep 7, 2017 |
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Hi,
I am using the PCIe testbench generated by the Quartus 9.1 Mega Wizard Plug in manager to verify my design which contains PCIe gen1 x8 core(Hard IP). we are using Arria IIgx family FPGA from Altera.From the documents provided by altera, the Root Port BFM and testbench cannot handle received read requests that are less than or equal to the currently set Maximum payload size.For example my PCIe Endpoint(RTL)the maximum payload size is 128 Bytes.So a read request of size greater than 128 Bytes is is not supported by the Root Port BFM. Can any one help me in solving this particular issue? I want to use 4KB as read request size. |
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RE: PCIe Testbench from Altera
by zhuzhu on Jul 21, 2010 |
zhuzhu
Posts: 21 Joined: Sep 22, 2009 Last seen: Sep 7, 2021 |
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hi,i'm also using the ip core provided with altera quartus9.1,but when i
verify the dma progamm generated by the ip megawizard with modelsim,there ar many errors,can anyone help me? |
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RE: PCIe Testbench from Altera
by zhuzhu on Jul 21, 2010 |
zhuzhu
Posts: 21 Joined: Sep 22, 2009 Last seen: Sep 7, 2021 |
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hi,i'm also using the ip core provided with altera quartus9.1,but when i
verify the dma progamm generated by the ip megawizard with modelsim,there ar many errors,can anyone help me? |
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RE: PCIe Testbench from Altera
by zhuzhu on Jul 21, 2010 |
zhuzhu
Posts: 21 Joined: Sep 22, 2009 Last seen: Sep 7, 2021 |
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hi,i'm also using the ip core provided with altera quartus9.1,but when i
verify the dma progamm generated by the ip megawizard with modelsim,there ar many errors,can anyone help me? |
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