



Meeting PCI timing with PCI Bridge
by batfink on Oct 26, 2010 |
batfink
Posts: 1 Joined: Aug 14, 2009 Last seen: Nov 19, 2015 |
||
Greetings
I am trying to specify the 28 ns toff (active drive to float time) for a Xilinx Spartan 3. The Xilinx documentation is off no help and following the example for the Xilinx PCI core results in errors. Does anybody have an example of a UCF file which can correctly constraint all timing for the Opencores PCI Bridge. Note that I have constrained successfully the tco, tsu and th. Many thanks |



