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PCI Target problems with burst write
by jorisvdv on Nov 11, 2010
jorisvdv
Posts: 3
Joined: Oct 12, 2010
Last seen: Jun 4, 2014
Let me start by saying that i'm very pleased with opencores and the people who are willing to share their IP.

For my study I am working on the interfacing of the PCI bus with memory in a FPGA,
with a Spartan 3 PCI evaluation board.

I'm using the PCI Target PCI32TLITE core available here on opencores (version R03)

I already found out that burst reads from the card are impossible, causing a relatively slow read performance, for this I'm planning on adding DMA to the design.

But according to the project description burst write transactions to the core should be possible. Unfortunally this doesn't seem to work, in simulation I'm getting a asserted STOP# signal if I keep FRAME# asserted to indicate a burst write to the core.

If I look at the statemachine (pciwbsequ.vhd) which translates the PCI transactions to whisbone transactions, it seems to me that it's impossible to accept burst write transactions, since STOP# will always be asserted in state S_DATA1 if FRAME# is asserted.

Is there anyone with experience or maybe even a solution to this problem?
RE: PCI Target problems with burst write
by sravanraja on Nov 12, 2010
sravanraja
Posts: 7
Joined: Jun 16, 2008
Last seen: Dec 27, 2018
Let me start by saying that i'm very pleased with opencores and the people who are willing to share their IP.

For my study I am working on the interfacing of the PCI bus with memory in a FPGA,
with a Spartan 3 PCI evaluation board.

I'm using the PCI Target PCI32TLITE core available here on opencores (version R03)

I already found out that burst reads from the card are impossible, causing a relatively slow read performance, for this I'm planning on adding DMA to the design.

But according to the project description burst write transactions to the core should be possible. Unfortunally this doesn't seem to work, in simulation I'm getting a asserted STOP# signal if I keep FRAME# asserted to indicate a burst write to the core.

If I look at the statemachine (pciwbsequ.vhd) which translates the PCI transactions to whisbone transactions, it seems to me that it's impossible to accept burst write transactions, since STOP# will always be asserted in state S_DATA1 if FRAME# is asserted.

Is there anyone with experience or maybe even a solution to this problem?


"please check trdy# is asseted when the frame is high along with irdy# , when you want to have a burst write/read ##.

along whith the stop# check the devsel# too."

you can get solution or idea form this situation else revert back the situation you come across.
RE: PCI Target problems with burst write
by sravanraja on Nov 12, 2010
sravanraja
Posts: 7
Joined: Jun 16, 2008
Last seen: Dec 27, 2018
please check trdy# is asseted when the frame is high along with irdy# , when you want to have a burst write/read ##.

along whith the stop# check the devsel# too.
RE: PCI Target problems with burst write
by peio on Nov 12, 2010
peio
Posts: 19
Joined: Nov 25, 2004
Last seen: Jan 20, 2022
Hi jorisvdv,

From the IP User's Manual:

"PCI BURST transactions are terminated by target with "termination with..." so burst transactions are
broken into individual transactions and they aren't traslated to whisbone bus as burst."

This IP is not designed for block peripherals. If you need burst at full speed consider using other PCI IP Core.

Regards,

Peio
RE: PCI Target problems with burst write
by jorisvdv on Nov 12, 2010
jorisvdv
Posts: 3
Joined: Oct 12, 2010
Last seen: Jun 4, 2014
Ok, I must have missed it in the manual, stupid of me, Thank you very much for your response. I shouldn't be a big problem, because I'm only going to use it for simple I/O commands.

I was just curious about implementing burst writes and I didn't get it to work, maybe I was doing something wrong, clearly this is by design.

As a base for my project it's still very well usable!
RE: PCI Target problems with burst write
by jorisvdv on Nov 12, 2010
jorisvdv
Posts: 3
Joined: Oct 12, 2010
Last seen: Jun 4, 2014
Ok, I must have missed it in the manual, stupid of me, Thank you very much for your response. I shouldn't be a big problem, because I'm only going to use it for simple I/O commands.

I was just curious about implementing burst writes and I didn't get it to work, maybe I was doing something wrong, clearly this is by design.

As a base for my project it's still very well usable!
RE: PCI Target problems with burst write
by peio on Nov 12, 2010
peio
Posts: 19
Joined: Nov 25, 2004
Last seen: Jan 20, 2022
Hi jorisvdv,

Thank you for your interest in the PCI Target IP Core. All comments contribute to improve this IP Core and Opencores in general.

Good luck with your project!.
RE: PCI Target problems with burst write
by o.behnam.o on Feb 1, 2012
o.behnam.o
Posts: 2
Joined: Jan 21, 2012
Last seen: Feb 3, 2012
Hi,

I want to build a PCI Intrface to read and write IO Space. I have a CPLD "EPM7128slc84-15" from ALTERA. Please help me what do I do ?

Thanks
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