can anyone help me in how to build pci and usb bridge

If you browse the OpenCores projects, you'll find the starting points that you need. You will find "PCI Target" and "PCI Bridge" under the heading "System Controller." You will find "USB 1.1 Host and Function IP core" under the heading "Communication Controller." The following assumes that you were asking about how to build a usb host controller. For the next step you might purchase the cheapest xilinx or altera pci form factor prototype board that they have on their websites, either one will do, about US$199.00, and use that to get a simple PCI function running with linux or windows or your OS of choice. If you don't get an fpga board, then you have to write a testbench and get everything debugged in simulation, that might be the best first step anway. The comments within Opencores the USBHostsave project indicate that it might work better on altera quartus, so check into that aspect first. Once you have debugged your PCI function, it's time to add your USB function. Write an HDL wrapper to connect the OpenCores USB design to your PCI design. If you're creating a USB host, you'll probably want it to act like one of the 3 following options: OHCI, EHCI, UHCI. If you want it to be an OTG device, then you should look into using an OTG PHY from phillips, ti or smsc instead of hard wiring your USB as only host or peripheral. Finally, you should go to usb.org and get the free download for "usb command verifier" to test your usb and ensure it's interoperable with other usb designs.

how can we controll the data transfer speed between the two devices..i am doing my final year project in this..can u explain in more clear way..

Here's one way to proceede: Download the cores and review the RTL and the documentation. Refer to page 3 of USBHostSlave_IPCore_Specification.pdf and to page 3 of PCI32tLite.pdf. Note that your PCI core and your USB core both have a wishbone interface. Then, refer to page 9 of the Wishbone B4 specification and note that the Wishbone handshaking protocol allows each IP core to throttle its data transfer speed. Now, go back and look at the diagram again on page 3 of PCI32tLite.pdf and you'll understand that what your asking about is how to replace the gh_uart_16550 in that diagram with the usbhostslave_ipcore. Now go look at page 24 of USBHostSlave_IPCore_Specification.pdf and it tells you how to connect up the wishbone bus. There's a waveform diagram on page 40 of wishbone spec B4 that shows you how to use Clock Edge 1 to throttle the cycle speed.