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PCIe on Virtex 5
by dspdassanayake on Oct 10, 2011
dspdassanayake
Posts: 3
Joined: Sep 25, 2010
Last seen: Oct 11, 2011
Hi all !!
I'm new to this forum.
I need to build a PCIe Core for Virtex 5 to read and write data from it's memory.
My development board is Xilinx XUPV5-LX110T.
I tried making it referring to the Xilinx example design but it didn't work.
I appreciate any help you can give as I'm on a tight deadline.
Thanks.
RE: PCIe on Virtex 5
by buenos on Oct 10, 2011
buenos
Posts: 15
Joined: Feb 5, 2008
Last seen: Aug 13, 2020
hi.
try my core, the PCIe_mini.
Its a lot simpler than the xilinx one. I have tried to use the xilinx example design, but it looks to me as a complete project for one particular application. the pcie_mini is an easily reusable core for other opencores project, connecting them through the standard wishbone bus.
regards, Istvan
RE: PCIe on Virtex 5
by dspdassanayake on Oct 10, 2011
dspdassanayake
Posts: 3
Joined: Sep 25, 2010
Last seen: Oct 11, 2011
Thank you very much for the reply.
Can you please tell me more about this Wishbone bus?
I'm really a beginner in this area and clueless about it.
Thanks in advance.
RE: PCIe on Virtex 5
by buenos on Oct 10, 2011
buenos
Posts: 15
Joined: Feb 5, 2008
Last seen: Aug 13, 2020
the wishbone bus is a very simple and easily useable bus interconnect system. The opencores community is mainly based on it. search the opencores website for the wishbone specs.

If you are an absolute beginner (as you said), you might want to implement something a lot simpler than this. You might be a genius, but I after 7 years of FPGA design experience dared to do a project like this. It involves timing constraints, manual clock network selection, clock domains, using multi-gigabit transceivers and other advanced FPGA stuff. Another option is to use the xilinx EDK to create a system with PCIe (a wizard), memory and so on, with using wizards... Then you dont need that much experience. The EDK does not work with my core, only with ilinx cores.

regards,
RE: PCIe on Virtex 5
by amigabill on Oct 10, 2011
amigabill
Posts: 34
Joined: Dec 14, 2008
Last seen: Oct 13, 2013
Can you please tell me more about this Wishbone bus?
I'm really a beginner in this area and clueless about it.


Go to opencores.org website

From menu at left choose HowTo/FAQ->Wishbone and you can download the specs from this page.
RE: PCIe on Virtex 5
by dspdassanayake on Oct 11, 2011
dspdassanayake
Posts: 3
Joined: Sep 25, 2010
Last seen: Oct 11, 2011


If you are an absolute beginner (as you said), you might want to implement something a lot simpler than this. You might be a genius, but I after 7 years of FPGA design experience dared to do a project like this. It involves timing constraints, manual clock network selection, clock domains, using multi-gigabit transceivers and other advanced FPGA stuff.


I know what you are saying. It's extremely difficult for me. But the problem is I didn't choose this. I was assigned to me as a part of a project. So there's no way I could skip doing this. Thanks a lot for the help. I'll read through the Wishbone info and get back to you guys.
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