no use no use 1/1 no use no use
PCIe Root Port for Vertix-5
by bromanous on Nov 3, 2011
Posts: 1
Joined: Nov 3, 2011
Last seen: Jan 25, 2018

I XUPv5 board and I need to provide The Vertix-5 with the functionality
of Root Port so that its able to finish Link Train with an Endpoint device

Xilinx only provide an Endpoint IP core for Vertix-5

Has any one worked on developing such a Root Port IP?

Thank you very much
no use no use 1/1 no use no use
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