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PCIe 3.0 Gen
by ravali on Feb 24, 2016
ravali
Posts: 3
Joined: Jan 9, 2016
Last seen: Jul 6, 2019

hiii
can anyone having PCIe3.0 gen verilog code with block diagram.send me to my mail ravali0805@gmail.com

RE: PCIe 3.0 Gen
by gokula41 on Jul 31, 2016
gokula41
Posts: 1
Joined: Apr 29, 2015
Last seen: Nov 15, 2016
plese send me the same to my mail gokulakrishnansekar93@gmail.com

i am looking to do a project in that.
RE: PCIe 3.0 Gen
by dgisselq on Jul 31, 2016
dgisselq
Posts: 245
Joined: Feb 20, 2015
Last seen: Oct 12, 2019
I would be glad to provide an OpenSource PCIe controller for you, allowing PCIe to interface with a local FPGA wishbone bus, however ... I'm still about $10k-$20k shy of the labour and materials I would need to do it. If you are willing to fund such an effort, please let me know.

Dan

RE: PCIe 3.0 Gen
by dgisselq on Aug 1, 2016
dgisselq
Posts: 245
Joined: Feb 20, 2015
Last seen: Oct 12, 2019
Have you evaluated whether or not the PCI Mini controller would work for your needs?

Dan

RE: PCIe 3.0 Gen
by olof on Aug 1, 2016
olof
Posts: 218
Joined: Feb 10, 2010
Last seen: Dec 17, 2018
Florent from Enjoy Digital has written a PCIe core in Migen, which is a python-based HDL that can generate verilog http://enjoy-digital.fr/cores.html

//Olof
RE: PCIe 3.0 Gen
by aborga on Nov 21, 2016
aborga
Posts: 23
Joined: Dec 15, 2008
Last seen: Oct 17, 2019
Have a look at: http://opencores.org/project,virtex7_pcie_dma

Cheers,
Andrea
RE: PCIe 3.0 Gen
by tamn on Feb 13, 2018
tamn
Posts: 1
Joined: Oct 9, 2017
Last seen: Mar 26, 2019
I would be glad to provide an OpenSource PCIe controller for you, allowing PCIe to interface with a local FPGA wishbone bus, however ... I'm still about $10k-$20k shy of the labour and materials I would need to do it. If you are willing to fund such an effort, please let me know.

Dan



Dan - can you contact me. I would like to discuss funding your project.
Chinh Le
ChinhL@lewiz.com
no use no use 1/1 no use no use
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