Hello there,

I would like to implement the Rx, Cpl and Tx engines for the PCIE Interface using lattice Diamond. As a newbie in VHDL I could not find any example Code or template especially for lattice Diamond. Is there anyone who has done something like that please you can help me with the VHDL Code. I don't need to implement the wishbone just the three engines.

Regards,

Hello again,

I just wanted to mention that I am using lattice Diamond(ECP5)for my Project I hope someone has implemented the different engines I am looking for using the ECP5.

Many thanks

Hello

I have not been able to implement the different engines. I really need your help just a simple one without Wishbone or AXI just a Transaction (TRN) will really help me. I think there might be someone who has some nice example template for lattice Diamond.

Many thanks

Good morning...

What is the application space you're trying to use this core in? Lattice licenses a PCIe IP core that should be pretty straightforward for you to use if the cores found here aren't sufficient to meet your needs... In fact, if I recall, the specific core isn't that expensive to license.

/jw

Hello Jw,

Thanks for your reply. Actually I have the IP core which is working properly. I have to implement the Rx and Tx engines in VHDL as the Interface with the different modules. As a newbie an example VHDL Code or a template will really help me to implement it. I think maybe someone has worked with it before and can help me with the code.
I hope you can help me
Many thanks

I'm confused by your response... If you have the Lattice PCIe IP core, then what, exactly, are you trying to do? When you say "Rx and Tx engines", what are you talking about?

Is this a school project?

/jw

Hello JW,

Thanks again for your Reply. Rx and Tx are the two Interfaces for transmit and receive TLP signal between the IP core and the module. You can have a look at the example model I have attached.

Many thanks