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Willing to join an on going project
by TDJ on Jun 14, 2020 |
TDJ
Posts: 4 Joined: May 23, 2020 Last seen: Jun 8, 2024 |
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Hello All,
I have completed my Bachelor's in Electronics Engineering and have completed an industrial training in Advanced RTL Design and Verification. I have good exposure to design and verification domain with the following qualifications: * Good understanding of the ASIC and FPGA design flow * Extensive experience in writing RTL models using Verilog HDL. * Good experience in writing Testbenches using SystemVerilog and UVM * Very good knowledge in verification methodologies * Experience in using industry standard EDA tools for the front-end design and verification. I am attaching here my Resume for further details about my skills and projects. I request you all to kindly give me an opportunity to contribute to your project. I would be very thankful and happy. Regards, Tasmai Joshi
Tasmai_D_Joshi.pdf (531 kb)
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RE: Willing to join an on going project
by buenos on Jun 14, 2020 |
buenos
Posts: 15 Joined: Feb 5, 2008 Last seen: Oct 13, 2024 |
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Hello,
My project was halted at the pre-testing phase. The code was modified from pcie_mini project that worked fine, to port it to the new Ultrascale series of fpgas. It was compiled, but not tested on a prototype. The work needed to be done is a full completion of the project, test it on a prototype, debug it and release new files directly to opencores. https://opencores.org/projects/pcie_mini_axi4s_wb If you are interested, contact me at buenos@opencores.org. You know opencores is free, that means you can download cores for free, and also NO ONE PAYS you a salary or fee for working on any opencores projects. Regards, |
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