Hi all I am trying to synthesize and implement the USB2.0 core on an FPGA , but it seems it needs large FPGA's (at least 200K gates), am using only 3 endpoints , is there a way to minimize the design more? I can implement maximum of 150K gates. thanks in advance. --------------------------------- Do you Yahoo!? Yahoo! Hotjobs: Enter the "Signing Bonus" Sweepstakes -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040109/d99ce232/attachment.htm

1... One Sugesstion which i could see is U may decrease on the memory or the fifo depth. -----Original Message----- From: Mohammad AK [mailto:perocletos@yahoo.com] Sent: Saturday, January 10, 2004 12:51 AM To: usb@opencores.org Subject: [usb] USB2.0 Hi all I am trying to synthesize and implement the USB2.0 core on an FPGA , but it seems it needs large FPGA's (at least 200K gates), am using only 3 endpoints , is there a way to minimize the design more? I can implement maximum of 150K gates. thanks in advance. _____ Do you Yahoo!? Yahoo! Hotjobs: Enter http://pa.yahoo.com/*http://us.rd.yahoo.com/hotjobs/mail_footer_email/evt=21482/*http://hotjobs.sweepstakes.yahoo.com/signingbonus> the "Signing Bonus" Sweepstakes -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040110/b2cf301a/attachment.htm

1. where can I find this FIFO , which .v file? 2. when I added the sources to the USB project it the hierarchy did not start only with usbf_top.v , the highest files were also the premitives.v and the usb_defines.v, and the synthesizer did not see the usb_defines, so I had to copy it's contents to the rest of the files ( *.v ) , and it worked perfectly but -as mentioned before - needs at least 200K FPGAs . I wanted to know whether this is the correct way of doing this synthesizing. besides minimizing the design more ! vi Kumar Krishnan ravikk@hexaware.com> wrote: 1... One Sugesstion which i could see is U may decrease on the memory or the fifo depth. -----Original Message----- From: Mohammad AK [mailto:perocletos@yahoo.com] Sent: Saturday, January 10, 2004 12:51 AM To: usb@opencores.org Subject: [usb] USB2.0 Hi all I am trying to synthesize and implement the USB2.0 core on an FPGA , but it seems it needs large FPGA's (at least 200K gates), am using only 3 endpoints , is there a way to minimize the design more? I can implement maximum of 150K gates. thanks in advance. --------------------------------- Do you Yahoo!? Yahoo! Hotjobs: Enter the "Signing Bonus" Sweepstakes_______________________________________________ http://www.opencores.org/mailman/listinfo/usb --------------------------------- Do you Yahoo!? Yahoo! Hotjobs: Enter the "Signing Bonus" Sweepstakes -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040110/e8d2ab4d/attachment.htm

On Sat, 2004-01-10 at 18:23, Mohammad AK wrote:


Hmm, there should NOT be a "primitives.v" file. You can
ignore that if it is in the CVS - it should'n be ...

The "usb_defines.v" is an include file. All you have to
do is to tell your synthesis tool where include files
are located and it should work just fine.


To "optimize" the design, you should very carefully read the usb_defines.v and the included documentation. There are no FIFOs used in the design (actually one, and it's already set to the absolute minimum (4 entries deep). Certainly reducing the memory size and number of endpoints will make it smaller. Getting a hold of a decent synthesis tool should help as well. The USB 2.0 function is about 20K ASIC (std. cell) gates. Typical ratio of FPGA to ASIC gates ranges in the 4-8 FPGA gates for each ASIC gate. So the numbers you are getting are about 20% higher than I would expect. You should also make sure you know exactly how to use your synthesis tool (trust me that is the case in 90% of all 'bad' results). Make sure the memory is constructed of BlockRams and NOT Flops or LUTs. Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/

Hi,
I am interested in your usb core, how many Luts or Logic elements did
it approximately need?
How have you tested your core?

kind regards, Harald Obereder