hello all , the USB1.1 core has 8 end points each needs around 42 PPins , ,so in order to reduce number of pins I removed the definition and any thing related to endpoints 3-7 (i.e I have now 0,1 and 2) , and I had no errors during synthesis, ,and it fitted on the FPGA I wanted (Xilinx Spartan 200K, PQ208 ), I havnt tested it yet but am I gonna have sth wrong here ? I changed nothing but the mentioned above. --------------------------------- Do you Yahoo!? Yahoo! Finance: Get your refund fast by filing online -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040209/e9add3b9/attachment.htm