1/1 
|
about USB1.1 core on FPGA
by Unknown on Feb 11, 2004 |
Not available! | ||
|
Hi everyone,
I am now trying to implement a USB 1.1 core on fpga using the USB1.1 core and PHY from opencores. In my hardware design, i connect FPGA to PDIUSB11 then to the USB cable. I would like to ask is it possible to implement PDIUSB11 on fpga? that mean do FPGA have the ability to do the part of PDIUSB11? Also, are the D+,D- 5V signals or 3.3 V signals ? While i am reading through the USB1.1 core , i don't understand why it can allow missing one J state in finding the synchronize pattern? Any reply will be appreciated. Thx a lot. Regards, TOM |
|||
|
about USB1.1 core on FPGA
by Unknown on Feb 11, 2004 |
Not available! | ||
|
From: usb-bounces@opencores.org [mailto:usb-bounces@opencores.org]On
Behalf Of tomko81@hotmail.com
Sent: Tuesday, February 10, 2004 6:22 PM
To: usb@opencores.org
Subject: [usb] about USB1.1 core on FPGA
I would like to ask is it possible to implement PDIUSB11 on fpga? that
mean do FPGA have the ability to do the part of PDIUSB11? Not if you want reliable operation. USB buffers are impedance matched and rise/fall time controlled
Also, are the D+,D- 5V signals or 3.3 V signals ?
Neither, read the spec, ch. 7. Marc Reinig System Solutions |
|||
1/1