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Design uses over 100 percent of one of the resources. USB11_CORE
by Unknown on Mar 4, 2004 |
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Hi Rudi,
Thanks for really quick reply! All I need to do is send a text(or a wave)
file to my eval FPGA board from a host PC and be able to retrieve it
back using USB comm. Thanks again for all your time!
Chad
----- Original Message -----
From: Rudolf Usselmannrudi@a...>
To:
Date: Thu Mar 4 04:27:25 CET 2004
Subject: [usb] Design uses over 100 percent of one of the
resources.
USB11_CORE
On Thu, 2004-03-04 at 10:19, chadpham@h... wrote:
> Hi all,
> After down load the usb1_core, I use WebPack 4.2 and Spartan2E eval
> board to build the project. But when I come to the point
> for "implement design" WebPack generated the error with the message
> "Design uses over 100 percent of one of the
resources." and more
> detail is
> "Number of External GCLKIOBs 1 out of 4 25% > Number of External IOBs 305 out of 142 214% > Number of LOCed External IOBs 0 out of 305 0% > Number of SLICEs 681 out of 2352 28% > Number of GCLKs 1 out of 4 25%" > Look like the IO was use more than it shoud be. Please give me some
> advices for this matter. Anything is appreciated!
> The question is did I add in the project something more than it should
> be? And we have to do more initialization than just download
and
> compile?
> Thank you all! Ohh, it's the IOs that are over used ... not FPGA gates .... Well, did you hock something up to the FIFOs ? How many end points did you configure ? Think about what you are doing, and read the error message very carefully ! What are you trying to achieve ? rudi ====================================================== ==
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