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Suspend mode and FPGA:s

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Suspend mode and FPGA:s by Unknown on Mar 4, 2004			Not available!
Hi! I would like to know how to implement an IP core in a FPGA or CPLD and still meet the requirement of maximum 500uA current consumprion in suspend mode. Is this really possible or are the cores not intended for bus powered devices? As far as I know there are no FPGA/CPLD that can run on 500uA. I'm thankful for any help! Hi! I would like to know how to implement an IP core in a FPGA or CPLD and still meet the requirement of maximum 500uA current consumprion in suspend mode. Is this really possible or are the cores not intended for bus powered devices? As far as I know there are no FPGA/CPLD that can run on 500uA. I'm thankful for any help!

Suspend mode and FPGA:s by Unknown on Mar 4, 2004			Not available!
At 11:24 AM 3/4/2004, you wrote: [q]Hi! I would like to know how to implement an IP core in a FPGA or CPLD and still meet the requirement of maximum 500uA current consumprion in suspend mode. Is this really possible or are the cores not intended for bus powered devices? As far as I know there are no FPGA/CPLD that can run on 500uA. I'm thankful for any help![/q] I think you are right about the FPGAs, there are none with idle currents this low. But you can always shut off the power to the FPGA and reload it when you need to power it back up. There are CPLDs with idle currents in the low uAs. I recall looking at a Coolrunner part, powered from 3.3 volts which had an idle current low enough that the quiescent current of the LDO was higher than the CPLD! I think the XCR3512 was around 10 to 20 uA or so. Can you fit your design in a CPLD though? Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL <A HREF="http://www.arius.com">http://www.arius.com</A> 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX At 11:24 AM 3/4/2004, you wrote: Hi! I would like to know how to implement an IP core in a FPGA or CPLD and still meet the requirement of maximum 500uA current consumprion in suspend mode. Is this really possible or are the cores not intended for bus powered devices? As far as I know there are no FPGA/CPLD that can run on 500uA. I'm thankful for any help! I think you are right about the FPGAs, there are none with idle currents this low. But you can always shut off the power to the FPGA and reload it when you need to power it back up. There are CPLDs with idle currents in the low uAs. I recall looking at a Coolrunner part, powered from 3.3 volts which had an idle current low enough that the quiescent current of the LDO was higher than the CPLD! I think the XCR3512 was around 10 to 20 uA or so. Can you fit your design in a CPLD though? Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
Thanks Rick! I think the core has to be up and running if it should be able to detect resume signaling from the hub? This does not make it easier though! Maybe I have to choose an integrated usb device controller instead... Anders Karlstrom ----- Original Message ----- From: Rick Collins<<A HREF="mailto:opencores.usb@a...">opencores.usb@a...</A>> To: Date: Thu Mar 4 20:40:09 CET 2004 Subject: [usb] Suspend mode and FPGA:s [q] At 11:24 AM 3/4/2004, you wrote: [q]>Hi! > >I would like to know how to implement an IP core in a FPGA or [/q] CPLD and [q]>still meet the requirement of maximum 500uA current consumprion [/q] in [q]>suspend mode. Is this really possible or are the cores not [/q] intended for [q]>bus powered devices? As far as I know there are no FPGA/CPLD [/q] that [q]>can run on 500uA. >I'm thankful for any help! [/q] I think you are right about the FPGAs, there are none with idle currents this low. But you can always shut off the power to the FPGA and reload it when you need to power it back up. There are CPLDs with idle currents in the low uAs. I recall looking at a Coolrunner part, powered from 3.3 volts which had an idle current low enough that the quiescent current of the LDO was higher than the CPLD! I think the XCR3512 was around 10 to 20 uA or so. Can you fit your design in a CPLD though? Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL <A HREF="http://www.arius.com">http://www.arius.com</A> 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX [/q] Thanks Rick! I think the core has to be up and running if it should be able to detect resume signaling from the hub? This does not make it easier though! Maybe I have to choose an integrated usb device controller instead... Anders Karlstrom ----- Original Message ----- From: Rick Collinsopencores.usb@a...> To: Date: Thu Mar 4 20:40:09 CET 2004 Subject: [usb] Suspend mode and FPGA:s At 11:24 AM 3/4/2004, you wrote: >Hi! > >I would like to know how to implement an IP core in a FPGA or CPLD and >still meet the requirement of maximum 500uA current consumprion in >suspend mode. Is this really possible or are the cores not intended for >bus powered devices? As far as I know there are no FPGA/CPLD that >can run on 500uA. >I'm thankful for any help! I think you are right about the FPGAs, there are none with idle currents this low. But you can always shut off the power to the FPGA and reload it when you need to power it back up. There are CPLDs with idle currents in the low uAs. I recall looking at a Coolrunner part, powered from 3.3 volts which had an idle current low enough that the quiescent current of the LDO was higher than the CPLD! I think the XCR3512 was around 10 to 20 uA or so. Can you fit your design in a CPLD though? Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
hello all, quote: [q] I think the core has to be up and running if it should be able to detect resume signaling from the hub? This does not make it easier though! [/q] unquote. i kinda have the same problem: since in my case the core will be running on a clock provided by the phy, putting the device in suspend will disable the clock, and thus the core wont be able to detect any resume signaling as well....right? will it be sufficient to just reset the core and usb bus when the clock is up & running after the bus (i will be using a clock manager in the fpga -> no problem generating a reset)? OR even better, will it be possible for me to tie suspend to the phy to 0 all the time? i want my device to work, it doesn't have to be up to the usb20 spec. if somebody can figure out what my options are, i would really appreciate some help on this point. thanks in advance, regards, Egwin Wesselink ----- Original Message ----- From: <A HREF="mailto:a_karlstrom@y...">a_karlstrom@y...</A><<A HREF="mailto:a_karlstrom@y...">a_karlstrom@y...</A>> To: Date: Fri Mar 5 12:37:41 CET 2004 Subject: [usb] Suspend mode and FPGA:s [q] Thanks Rick! I think the core has to be up and running if it should be able to detect resume signaling from the hub? This does not make it easier though! Maybe I have to choose an integrated usb device controller instead... Anders Karlstrom ----- Original Message ----- From: Rick Collins<<A HREF="mailto:opencores.usb@a...">opencores.usb@a...</A>> To: Date: Thu Mar 4 20:40:09 CET 2004 Subject: [usb] Suspend mode and FPGA:s [q]> At 11:24 AM 3/4/2004, you wrote: [q] >Hi! > >I would like to know how to implement an IP core in a FPGA [/q] or [q]> CPLD and [q] >still meet the requirement of maximum 500uA current [/q] consumprion [q]> in [q] >suspend mode. Is this really possible or are the cores not [/q] > intended for [q] >bus powered devices? As far as I know there are no [/q] FPGA/CPLD [q]> that [q] >can run on 500uA. >I'm thankful for any help! [/q] > I think you are right about the FPGAs, there are none with [/q] idle [q]> currents > this low. But you can always shut off the power to the FPGA [/q] and [q]> reload it > when you need to power it back up. > There are CPLDs with idle currents in the low uAs. I recall [/q] looking [q]> at a > Coolrunner part, powered from 3.3 volts which had an idle [/q] current [q]> low > enough that the quiescent current of the LDO was higher than [/q] the [q]> CPLD! I > think the XCR3512 was around 10 to 20 uA or so. Can you fit [/q] your [q]> design in > a CPLD though? > Rick Collins > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL <A HREF="http://www.arius.com">http://www.arius.com</A> > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX > > [/q] [/q] hello all, quote: I think the core has to be up and running if it should be able to detect resume signaling from the hub? This does not make it easier though! unquote. i kinda have the same problem: since in my case the core will be running on a clock provided by the phy, putting the device in suspend will disable the clock, and thus the core wont be able to detect any resume signaling as well....right? will it be sufficient to just reset the core and usb bus when the clock is up & running after the bus (i will be using a clock manager in the fpga -> no problem generating a reset)? OR even better, will it be possible for me to tie suspend to the phy to 0 all the time? i want my device to work, it doesn't have to be up to the usb20 spec. if somebody can figure out what my options are, i would really appreciate some help on this point. thanks in advance, regards, Egwin Wesselink ----- Original Message ----- From: a_karlstrom@y...a_karlstrom@y...> To: Date: Fri Mar 5 12:37:41 CET 2004 Subject: [usb] Suspend mode and FPGA:s Thanks Rick! I think the core has to be up and running if it should be able to detect resume signaling from the hub? This does not make it easier though! Maybe I have to choose an integrated usb device controller instead... Anders Karlstrom ----- Original Message ----- From: Rick Collinsopencores.usb@a...> To: Date: Thu Mar 4 20:40:09 CET 2004 Subject: [usb] Suspend mode and FPGA:s > At 11:24 AM 3/4/2004, you wrote: >Hi! > >I would like to know how to implement an IP core in a FPGA or > CPLD and >still meet the requirement of maximum 500uA current consumprion > in >suspend mode. Is this really possible or are the cores not > intended for >bus powered devices? As far as I know there are no FPGA/CPLD > that >can run on 500uA. >I'm thankful for any help! > I think you are right about the FPGAs, there are none with idle > currents > this low. But you can always shut off the power to the FPGA and > reload it > when you need to power it back up. > There are CPLDs with idle currents in the low uAs. I recall looking > at a > Coolrunner part, powered from 3.3 volts which had an idle current > low > enough that the quiescent current of the LDO was higher than the > CPLD! I > think the XCR3512 was around 10 to 20 uA or so. Can you fit your > design in > a CPLD though? > Rick Collins > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX > >

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
At 10:10 AM 3/5/2004, you wrote: [q]hello all, quote: [q]> I think the core has to be up and running if it should be able to detect > resume signaling from the hub? This does not make it easier though![/q] unquote. i kinda have the same problem: since in my case the core will be running on a clock provided by the phy, putting the device in suspend will disable the clock, and thus the core wont be able to detect any resume signaling as well....right? will it be sufficient to just reset the core and usb bus when the clock is up & running after the bus (i will be using a clock manager in the fpga -> no problem generating a reset)? OR even better, will it be possible for me to tie suspend to the phy to 0 all the time? i want my device to work, it doesn't have to be up to the usb20 spec. if somebody can figure out what my options are, i would really appreciate some help on this point.[/q] If you want to put the FPGA in a very low power mode, you will have to pick your FPGA for that. I have been doing a lot of searching for semi-low power, but mainly 5 volt tolerant FPGAs. Turns out there is a lot of overlap between the two. As they shrink the process geometries, the 5 volt tolerance goes away and the quiescent current goes up. I found an ACEX (EP1Kxx) family from Altera that has 5 volt tolerance with a quiescent current in the 5 - 10 mA range. This is not within your spec, but it may do the job. Altera also makes the Cyclone family (EP1Cxx) which is not 5 volt tolerant and has a quiescent current in the 4 - 12 mA range (typ) depending on part. Xilinx lost 5 volt tolerance with the introduction of the Virtex IIE family. The quiescent current of the Virtex IIE is in the 100's of mA. The Virtex II family has 5 volt tolerance and has a quiescent current around 10 - 100 mA depending on the part. The older Spartan XL family is both 5 volt tolerant and has a very low quiescent current of about 100 uA. Certainly it will be easier to work with the newer parts since they also tend to be cheaper and larger. But the older parts fit your needs better it seems. What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus? Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL <A HREF="http://www.arius.com">http://www.arius.com</A> 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX At 10:10 AM 3/5/2004, you wrote: hello all, quote: > I think the core has to be up and running if it should be able to detect > resume signaling from the hub? This does not make it easier though! unquote. i kinda have the same problem: since in my case the core will be running on a clock provided by the phy, putting the device in suspend will disable the clock, and thus the core wont be able to detect any resume signaling as well....right? will it be sufficient to just reset the core and usb bus when the clock is up & running after the bus (i will be using a clock manager in the fpga -> no problem generating a reset)? OR even better, will it be possible for me to tie suspend to the phy to 0 all the time? i want my device to work, it doesn't have to be up to the usb20 spec. if somebody can figure out what my options are, i would really appreciate some help on this point. If you want to put the FPGA in a very low power mode, you will have to pick your FPGA for that. I have been doing a lot of searching for semi-low power, but mainly 5 volt tolerant FPGAs. Turns out there is a lot of overlap between the two. As they shrink the process geometries, the 5 volt tolerance goes away and the quiescent current goes up. I found an ACEX (EP1Kxx) family from Altera that has 5 volt tolerance with a quiescent current in the 5 - 10 mA range. This is not within your spec, but it may do the job. Altera also makes the Cyclone family (EP1Cxx) which is not 5 volt tolerant and has a quiescent current in the 4 - 12 mA range (typ) depending on part. Xilinx lost 5 volt tolerance with the introduction of the Virtex IIE family. The quiescent current of the Virtex IIE is in the 100's of mA. The Virtex II family has 5 volt tolerance and has a quiescent current around 10 - 100 mA depending on the part. The older Spartan XL family is both 5 volt tolerant and has a very low quiescent current of about 100 uA. Certainly it will be easier to work with the newer parts since they also tend to be cheaper and larger. But the older parts fit your needs better it seems. What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus? Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
At 10:39 AM 3/5/2004, you wrote: [q]If you want to put the FPGA in a very low power mode, you will have to pick your FPGA for that. I have been doing a lot of searching for semi-low power, but mainly 5 volt tolerant FPGAs. Turns out there is a lot of overlap between the two. As they shrink the process geometries, the 5 volt tolerance goes away and the quiescent current goes up. I found an ACEX (EP1Kxx) family from Altera that has 5 volt tolerance with a quiescent current in the 5 - 10 mA range. This is not within your spec, but it may do the job. Altera also makes the Cyclone family (EP1Cxx) which is not 5 volt tolerant and has a quiescent current in the 4 - 12 mA range (typ) depending on part. Xilinx lost 5 volt tolerance with the introduction of the Virtex IIE family. The quiescent current of the Virtex IIE is in the 100's of mA. The Virtex II family has 5 volt tolerance and has a quiescent current around 10 - 100 mA depending on the part. The older Spartan XL family is both 5 volt tolerant and has a very low quiescent current of about 100 uA. Certainly it will be easier to work with the newer parts since they also tend to be cheaper and larger. But the older parts fit your needs better it seems. What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus?[/q] Sorry, all of my references to Virtex above should be changed to Spartan. Xilinx introduced the Spartan family as a low cost version of the XC4000 family. Then the low cost version of the Virtex/Virtex E family was the Spartan II/IIE and now the low cost version of the Virtex II family is the Spartan 3. I was looking at the Spartan II/IIE data sheets and wrote Virtex II/IIE. I don't even think there is a Virtex IIE family. :) Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL <A HREF="http://www.arius.com">http://www.arius.com</A> 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX At 10:39 AM 3/5/2004, you wrote: If you want to put the FPGA in a very low power mode, you will have to pick your FPGA for that. I have been doing a lot of searching for semi-low power, but mainly 5 volt tolerant FPGAs. Turns out there is a lot of overlap between the two. As they shrink the process geometries, the 5 volt tolerance goes away and the quiescent current goes up. I found an ACEX (EP1Kxx) family from Altera that has 5 volt tolerance with a quiescent current in the 5 - 10 mA range. This is not within your spec, but it may do the job. Altera also makes the Cyclone family (EP1Cxx) which is not 5 volt tolerant and has a quiescent current in the 4 - 12 mA range (typ) depending on part. Xilinx lost 5 volt tolerance with the introduction of the Virtex IIE family. The quiescent current of the Virtex IIE is in the 100's of mA. The Virtex II family has 5 volt tolerance and has a quiescent current around 10 - 100 mA depending on the part. The older Spartan XL family is both 5 volt tolerant and has a very low quiescent current of about 100 uA. Certainly it will be easier to work with the newer parts since they also tend to be cheaper and larger. But the older parts fit your needs better it seems. What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus? Sorry, all of my references to Virtex above should be changed to Spartan. Xilinx introduced the Spartan family as a low cost version of the XC4000 family. Then the low cost version of the Virtex/Virtex E family was the Spartan II/IIE and now the low cost version of the Virtex II family is the Spartan 3. I was looking at the Spartan II/IIE data sheets and wrote Virtex II/IIE. I don't even think there is a Virtex IIE family. :) Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
first of all thanks for the quick reply The info you gave me is very usefull, i know now i wont be able to implement suspend/resume. i will have to be working on an xilinx virtex II 8000. Though that's not that big of a punishment :-), it draws too much power. i think i'm gonna NOT suspend my device at all (though not up to spec) since it isn't powered by the usb bus. (for a quick reference to my project (if you're interested) see the bumped post i did couple of days ago). If i wont suspend it, it'll respond to resume signaling nonetheless since my core's still up and running...right? i'll have to check whether it is at all possible to not suspend a device, though in my case i think there aren't too many other options. quote [q] What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus? [/q] unquote i think i wont be able to implement the suspend mode because of this too, since even when the phy wakes up on the first signal transition, my DCM in the FPGA will still need time to lock. i just found out my phy isn't bus powered too so not suspending the device wont be a problem i guess... Regards, Egwin Wesselink ----- Original Message ----- From: Rick Collins<<A HREF="mailto:opencores.usb@a...">opencores.usb@a...</A>> To: Date: Fri Mar 5 16:39:30 CET 2004 Subject: [usb] Suspend mode and FPGA:s [q] At 10:10 AM 3/5/2004, you wrote: [q]>hello all, > >quote: [q] > I think the core has to be up and running if it should be [/q] able to detect [q] > resume signaling from the hub? This does not make it [/q] easier though! [q]>unquote. >i kinda have the same problem: >since in my case the core will be running on a clock provided [/q] by the [q]>phy, putting the device in suspend will disable the clock, and [/q] thus the [q]>core wont be able to detect any resume signaling as [/q] well....right? [q]> >will it be sufficient to just reset the core and usb bus when [/q] the clock is [q]>up & running after the bus (i will be using a clock manager [/q] in the fpga -> [q]>no problem generating a reset)? > >OR even better, will it be possible for me to tie suspend to [/q] the phy to 0 [q]>all the time? i want my device to work, it doesn't have to be [/q] up to the [q]>usb20 spec. > >if somebody can figure out what my options are, i would really >appreciate some help on this point. [/q] If you want to put the FPGA in a very low power mode, you will have to pick your FPGA for that. I have been doing a lot of searching for semi-low power, but mainly 5 volt tolerant FPGAs. Turns out there is a lot of overlap between the two. As they shrink the process geometries, the 5 volt tolerance goes away and the quiescent current goes up. I found an ACEX (EP1Kxx) family from Altera that has 5 volt tolerance with a quiescent current in the 5 - 10 mA range. This is not within your spec, but it may do the job. Altera also makes the Cyclone family (EP1Cxx) which is not 5 volt tolerant and has a quiescent current in the 4 - 12 mA range (typ) depending on part. Xilinx lost 5 volt tolerance with the introduction of the Virtex IIE family. The quiescent current of the Virtex IIE is in the 100's of mA. The Virtex II family has 5 volt tolerance and has a quiescent current around 10 - 100 mA depending on the part. The older Spartan XL family is both 5 volt tolerant and has a very low quiescent current of about 100 uA. Certainly it will be easier to work with the newer parts since they also tend to be cheaper and larger. But the older parts fit your needs better it seems. What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus? Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL <A HREF="http://www.arius.com">http://www.arius.com</A> 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX [/q] first of all thanks for the quick reply The info you gave me is very usefull, i know now i wont be able to implement suspend/resume. i will have to be working on an xilinx virtex II 8000. Though that's not that big of a punishment :-), it draws too much power. i think i'm gonna NOT suspend my device at all (though not up to spec) since it isn't powered by the usb bus. (for a quick reference to my project (if you're interested) see the bumped post i did couple of days ago). If i wont suspend it, it'll respond to resume signaling nonetheless since my core's still up and running...right? i'll have to check whether it is at all possible to not suspend a device, though in my case i think there aren't too many other options. quote What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus? unquote i think i wont be able to implement the suspend mode because of this too, since even when the phy wakes up on the first signal transition, my DCM in the FPGA will still need time to lock. i just found out my phy isn't bus powered too so not suspending the device wont be a problem i guess... Regards, Egwin Wesselink ----- Original Message ----- From: Rick Collinsopencores.usb@a...> To: Date: Fri Mar 5 16:39:30 CET 2004 Subject: [usb] Suspend mode and FPGA:s At 10:10 AM 3/5/2004, you wrote: >hello all, > >quote: > I think the core has to be up and running if it should be able to detect > resume signaling from the hub? This does not make it easier though! >unquote. >i kinda have the same problem: >since in my case the core will be running on a clock provided by the >phy, putting the device in suspend will disable the clock, and thus the >core wont be able to detect any resume signaling as well....right? > >will it be sufficient to just reset the core and usb bus when the clock is >up & running after the bus (i will be using a clock manager in the fpga -> >no problem generating a reset)? > >OR even better, will it be possible for me to tie suspend to the phy to 0 >all the time? i want my device to work, it doesn't have to be up to the >usb20 spec. > >if somebody can figure out what my options are, i would really >appreciate some help on this point. If you want to put the FPGA in a very low power mode, you will have to pick your FPGA for that. I have been doing a lot of searching for semi-low power, but mainly 5 volt tolerant FPGAs. Turns out there is a lot of overlap between the two. As they shrink the process geometries, the 5 volt tolerance goes away and the quiescent current goes up. I found an ACEX (EP1Kxx) family from Altera that has 5 volt tolerance with a quiescent current in the 5 - 10 mA range. This is not within your spec, but it may do the job. Altera also makes the Cyclone family (EP1Cxx) which is not 5 volt tolerant and has a quiescent current in the 4 - 12 mA range (typ) depending on part. Xilinx lost 5 volt tolerance with the introduction of the Virtex IIE family. The quiescent current of the Virtex IIE is in the 100's of mA. The Virtex II family has 5 volt tolerance and has a quiescent current around 10 - 100 mA depending on the part. The older Spartan XL family is both 5 volt tolerant and has a very low quiescent current of about 100 uA. Certainly it will be easier to work with the newer parts since they also tend to be cheaper and larger. But the older parts fit your needs better it seems. What exactly is the wake up criteria in the USB spec? It would be an unusual circuit that could do significant processing and still have very low power like this (500 uA). But then I guess it is not impossible. Does the circuit wake up on the first signal transition on the USB bus? Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
At 11:17 AM 3/5/2004, you wrote: [q]first of all thanks for the quick reply The info you gave me is very usefull, i know now i wont be able to implement suspend/resume. i will have to be working on an xilinx virtex II 8000. Though that's not that big of a punishment :-), it draws too much power.[/q] That is a really large part. I will be surprised if you could get that to run off the USB power anyway since it is limited to 2.5 Watts. If you are using half of this FPGA and running it at much speed, it will use more than this easily. [q]i think i'm gonna NOT suspend my device at all (though not up to spec) since it isn't powered by the usb bus. (for a quick reference to my project (if you're interested) see the bumped post i did couple of days ago). If i wont suspend it, it'll respond to resume signaling nonetheless since my core's still up and running...right?[/q] I don't know the USB spec, but it should work ok. I looked at your post and I don't see where you ever got a response. Did you get the interface issue straightened out? [q]i'll have to check whether it is at all possible to not suspend a device, though in my case i think there aren't too many other options. quote [q]> What exactly is the wake up criteria in the USB spec? It would be > an > unusual circuit that could do significant processing and still have > very > low power like this (500 uA). But then I guess it is not > impossible. Does > the circuit wake up on the first signal transition on the USB bus?[/q] unquote i think i wont be able to implement the suspend mode because of this too, since even when the phy wakes up on the first signal transition, my DCM in the FPGA will still need time to lock. i just found out my phy isn't bus powered too so not suspending the device wont be a problem i guess...[/q] I am sure the spec allows for devices that don't actually power down if they are not on USB power. A printer is a good example, they don't power down at all other than when they decide to. Even then I am sure they are really powered up still, just the motors are off. I am pretty sure the suspend state is intended to be done by custom chips where you can control power much more easily. We are designing a new DSP board which uses an FPGA and daughter cards to add IO capability. I belive the USB2.0 core you are looking at is a slave only. We would like to implement a master/slave device, likely OTG, using the FPGA and a PHY like you are doing. Any ideas on how to do this? Do you know of anyone working on a USB 2.0 (high speed) OTG core? I have not found any ASSP chips for this either. All the OTG chips seem to be full speed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL <A HREF="http://www.arius.com">http://www.arius.com</A> 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX At 11:17 AM 3/5/2004, you wrote: first of all thanks for the quick reply The info you gave me is very usefull, i know now i wont be able to implement suspend/resume. i will have to be working on an xilinx virtex II 8000. Though that's not that big of a punishment :-), it draws too much power. That is a really large part. I will be surprised if you could get that to run off the USB power anyway since it is limited to 2.5 Watts. If you are using half of this FPGA and running it at much speed, it will use more than this easily. i think i'm gonna NOT suspend my device at all (though not up to spec) since it isn't powered by the usb bus. (for a quick reference to my project (if you're interested) see the bumped post i did couple of days ago). If i wont suspend it, it'll respond to resume signaling nonetheless since my core's still up and running...right? I don't know the USB spec, but it should work ok. I looked at your post and I don't see where you ever got a response. Did you get the interface issue straightened out? i'll have to check whether it is at all possible to not suspend a device, though in my case i think there aren't too many other options. quote > What exactly is the wake up criteria in the USB spec? It would be > an > unusual circuit that could do significant processing and still have > very > low power like this (500 uA). But then I guess it is not > impossible. Does > the circuit wake up on the first signal transition on the USB bus? unquote i think i wont be able to implement the suspend mode because of this too, since even when the phy wakes up on the first signal transition, my DCM in the FPGA will still need time to lock. i just found out my phy isn't bus powered too so not suspending the device wont be a problem i guess... I am sure the spec allows for devices that don't actually power down if they are not on USB power. A printer is a good example, they don't power down at all other than when they decide to. Even then I am sure they are really powered up still, just the motors are off. I am pretty sure the suspend state is intended to be done by custom chips where you can control power much more easily. We are designing a new DSP board which uses an FPGA and daughter cards to add IO capability. I belive the USB2.0 core you are looking at is a slave only. We would like to implement a master/slave device, likely OTG, using the FPGA and a PHY like you are doing. Any ideas on how to do this? Do you know of anyone working on a USB 2.0 (high speed) OTG core? I have not found any ASSP chips for this either. All the OTG chips seem to be full speed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
On Fri, 2004-03-05 at 23:17, <A HREF="mailto:wesselin@natlab.research.philips.com">wesselin@natlab.research.philips.com</A> wrote: [q] first of all thanks for the quick reply The info you gave me is very usefull, i know now i wont be able to implement suspend/resume. i will have to be working on an xilinx virtex II 8000. Though that's not that big of a punishment :-), it draws too much power. i think i'm gonna NOT suspend my device at all (though not up to spec) since it isn't powered by the usb bus. (for a quick reference to my project (if you're interested) see the bumped post i did couple of days ago). If i wont suspend it, it'll respond to resume signaling nonetheless since my core's still up and running...right? i'll have to check whether it is at all possible to not suspend a device, though in my case i think there aren't too many other options.[/q] All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. And, yes, you should follow the protocol, and perhaps signal to your local logic that you have receives a suspend event. After all that means that you will not be getting any traffic from the usb bus, so you might want to 'notice' that event. Same for resume signaling, you should 'notice' the event, and get back in to the 'working' state, but since you are self powered, you don't have to turn off power or even place the PHY in to the suspend mode. If you do suspend the PHY, you must have a combinatorial path to wake it up, as the clock will be turned off. That is usually done by wathing the LineStat signals (which become combinatorial path inside the PHY when you suspend the PHY). If the state of LineState changes, you automatically start wake up and resume ... [q] quote [q]> What exactly is the wake up criteria in the USB spec? It would be > an > unusual circuit that could do significant processing and still have > very > low power like this (500 uA). But then I guess it is not > impossible. Does > the circuit wake up on the first signal transition on the USB bus? [/q] unquote i think i wont be able to implement the suspend mode because of this too, since even when the phy wakes up on the first signal transition, my DCM in the FPGA will still need time to lock. i just found out my phy isn't bus powered too so not suspending the device wont be a problem i guess... Regards, Egwin Wesselink[/q] Cheers, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <- FREE EDA Tools On Fri, 2004-03-05 at 23:17, wesselin@natlab.research.philips.com wrote: first of all thanks for the quick reply The info you gave me is very usefull, i know now i wont be able to implement suspend/resume. i will have to be working on an xilinx virtex II 8000. Though that's not that big of a punishment :-), it draws too much power. i think i'm gonna NOT suspend my device at all (though not up to spec) since it isn't powered by the usb bus. (for a quick reference to my project (if you're interested) see the bumped post i did couple of days ago). If i wont suspend it, it'll respond to resume signaling nonetheless since my core's still up and running...right? i'll have to check whether it is at all possible to not suspend a device, though in my case i think there aren't too many other options. All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. And, yes, you should follow the protocol, and perhaps signal to your local logic that you have receives a suspend event. After all that means that you will not be getting any traffic from the usb bus, so you might want to 'notice' that event. Same for resume signaling, you should 'notice' the event, and get back in to the 'working' state, but since you are self powered, you don't have to turn off power or even place the PHY in to the suspend mode. If you do suspend the PHY, you must have a combinatorial path to wake it up, as the clock will be turned off. That is usually done by wathing the LineStat signals (which become combinatorial path inside the PHY when you suspend the PHY). If the state of LineState changes, you automatically start wake up and resume ... quote > What exactly is the wake up criteria in the USB spec? It would be > an > unusual circuit that could do significant processing and still have > very > low power like this (500 uA). But then I guess it is not > impossible. Does > the circuit wake up on the first signal transition on the USB bus? unquote i think i wont be able to implement the suspend mode because of this too, since even when the phy wakes up on the first signal transition, my DCM in the FPGA will still need time to lock. i just found out my phy isn't bus powered too so not suspending the device wont be a problem i guess... Regards, Egwin Wesselink Cheers, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/

Suspend mode and FPGA:s by Unknown on Mar 5, 2004			Not available!
Hi Rudolf! quote All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. unquote What if you are bus-powered, and still want some pizza? :) Is it possible to use any of your cores and be able to suspend/resume as specified? Or do I have to choose an integrated usb device controller instead? Regards, Anders KarlstrÃ¶m Hi Rudolf! quote All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. unquote What if you are bus-powered, and still want some pizza? :) Is it possible to use any of your cores and be able to suspend/resume as specified? Or do I have to choose an integrated usb device controller instead? Regards, Anders KarlstrÃ¶m

Suspend mode and FPGA:s by Unknown on Mar 6, 2004			Not available!
On Sat, 2004-03-06 at 01:24, =?us-ascii?Q?Anders Karlstr=F6m?= wrote: [q] Hi Rudolf! quote All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. unquote What if you are bus-powered, and still want some pizza? :)[/q] Then, .... you are out of luck ! [q] Is it possible to use any of your cores and be able to suspend/resume as specified? Or do I have to choose an integrated usb device controller instead?[/q] The USB 1.1 IP does not support any of these features. It's purpose was a small and simple solution. However, USB 2.0 IP was designed to support it. [q] Regards, Anders Karlstrm[/q] Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <- FREE EDA Tools On Sat, 2004-03-06 at 01:24, =?us-ascii?Q?Anders Karlstr=F6m?= wrote: Hi Rudolf! quote All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. unquote What if you are bus-powered, and still want some pizza? :) Then, .... you are out of luck ! Is it possible to use any of your cores and be able to suspend/resume as specified? Or do I have to choose an integrated usb device controller instead? The USB 1.1 IP does not support any of these features. It's purpose was a small and simple solution. However, USB 2.0 IP was designed to support it. Regards, Anders Karlstrm Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/

Suspend mode and FPGA:s by Unknown on Mar 8, 2004			Not available!
thanks for the input, i think i'm gonna not suspend my phy and teach my fpga to bake some pizza....... regards, Egwin All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. And, yes, you should follow the protocol, and perhaps signal to your local logic that you have receives a suspend event. After all that means that you will not be getting any traffic from the usb bus, so you might want to 'notice' that event. Same for resume signaling, you should 'notice' the event, and get back in to the 'working' state, but since you are self powered, you don't have to turn off power or even place the PHY in to the suspend mode. ----- Original Message ----- From: Rudolf Usselmann<<A HREF="mailto:rudi@a...">rudi@a...</A>> To: Date: Fri Mar 5 18:31:41 CET 2004 Subject: [usb] Suspend mode and FPGA:s [q] On Fri, 2004-03-05 at 23:17, <A HREF="mailto:wesselin@n...">wesselin@n...</A> wrote: [q]> first of all thanks for the quick reply > > The info you gave me is very usefull, i know now i wont be [/q] able to [q]> implement suspend/resume. > i will have to be working on an xilinx virtex II 8000. Though [/q] that's not [q]> that big of a punishment :-), it draws too much power. > > i think i'm gonna NOT suspend my device at all (though not up [/q] to spec) [q]> since it isn't powered by the usb bus. (for a quick reference [/q] to my [q]> project (if you're interested) see the bumped post i did [/q] couple of days [q]> ago). If i wont suspend it, it'll respond to resume signaling [/q] nonetheless [q]> since my core's still up and running...right? > > i'll have to check whether it is at all possible to not [/q] suspend a device, [q]> though in my case i think there aren't too many other options. [/q] All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. And, yes, you should follow the protocol, and perhaps signal to your local logic that you have receives a suspend event. After all that means that you will not be getting any traffic from the usb bus, so you might want to 'notice' that event. Same for resume signaling, you should 'notice' the event, and get back in to the 'working' state, but since you are self powered, you don't have to turn off power or even place the PHY in to the suspend mode. If you do suspend the PHY, you must have a combinatorial path to wake it up, as the clock will be turned off. That is usually done by wathing the LineStat signals (which become combinatorial path inside the PHY when you suspend the PHY). If the state of LineState changes, you automatically start wake up and resume ... [q]> quote [q] > What exactly is the wake up criteria in the USB spec? It [/q] would be [q] > an > unusual circuit that could do significant processing and [/q] still have [q] > very > low power like this (500 uA). But then I guess it is not > impossible. Does > the circuit wake up on the first signal transition on the [/q] USB bus? [q]> unquote > > i think i wont be able to implement the suspend mode because [/q] of this [q]> too, since even when the phy wakes up on the first signal [/q] transition, my [q]> DCM in the FPGA will still need time to lock. > > i just found out my phy isn't bus powered too so not [/q] suspending the [q]> device wont be a problem i guess... > > Regards, > > Egwin Wesselink [/q] Cheers, rudi [/q] ====================================================== == [q] ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> <A HREF="http://www.asics.ws/">http://www.asics.ws/</A> <- FREE EDA Tools [/q] thanks for the input, i think i'm gonna not suspend my phy and teach my fpga to bake some pizza....... regards, Egwin All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. And, yes, you should follow the protocol, and perhaps signal to your local logic that you have receives a suspend event. After all that means that you will not be getting any traffic from the usb bus, so you might want to 'notice' that event. Same for resume signaling, you should 'notice' the event, and get back in to the 'working' state, but since you are self powered, you don't have to turn off power or even place the PHY in to the suspend mode. ----- Original Message ----- From: Rudolf Usselmannrudi@a...> To: Date: Fri Mar 5 18:31:41 CET 2004 Subject: [usb] Suspend mode and FPGA:s On Fri, 2004-03-05 at 23:17, wesselin@n... wrote: > first of all thanks for the quick reply > > The info you gave me is very usefull, i know now i wont be able to > implement suspend/resume. > i will have to be working on an xilinx virtex II 8000. Though that's not > that big of a punishment :-), it draws too much power. > > i think i'm gonna NOT suspend my device at all (though not up to spec) > since it isn't powered by the usb bus. (for a quick reference to my > project (if you're interested) see the bumped post i did couple of days > ago). If i wont suspend it, it'll respond to resume signaling nonetheless > since my core's still up and running...right? > > i'll have to check whether it is at all possible to not suspend a device, > though in my case i think there aren't too many other options. All that suspend means is that you must not draw any power from the USB bus. If you are self-powered, you can bake pizza on the side and be compliant. And, yes, you should follow the protocol, and perhaps signal to your local logic that you have receives a suspend event. After all that means that you will not be getting any traffic from the usb bus, so you might want to 'notice' that event. Same for resume signaling, you should 'notice' the event, and get back in to the 'working' state, but since you are self powered, you don't have to turn off power or even place the PHY in to the suspend mode. If you do suspend the PHY, you must have a combinatorial path to wake it up, as the clock will be turned off. That is usually done by wathing the LineStat signals (which become combinatorial path inside the PHY when you suspend the PHY). If the state of LineState changes, you automatically start wake up and resume ... > quote > What exactly is the wake up criteria in the USB spec? It would be > an > unusual circuit that could do significant processing and still have > very > low power like this (500 uA). But then I guess it is not > impossible. Does > the circuit wake up on the first signal transition on the USB bus? > unquote > > i think i wont be able to implement the suspend mode because of this > too, since even when the phy wakes up on the first signal transition, my > DCM in the FPGA will still need time to lock. > > i just found out my phy isn't bus powered too so not suspending the > device wont be a problem i guess... > > Regards, > > Egwin Wesselink Cheers, rudi ====================================================== == ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/

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