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- Mode should be hard wired
- Suspend should go to the FPGA (if you are planning to
use it, otherwise hardwire as ell).
- Why do you use 10K resistors between the FPGA and the
transceiver ?



On Tue, 2004-03-09 at 01:34, Mohammad AK wrote:
-- rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/

According to the USB spec., you are not supposed to source any current when Vusb is not present. You need to gate your connection between the 3.3 V (J3 - 5) and R10 with Vusb. Marc Reinig System Solutions -----Original Message----- From: usb-bounces@opencores.org [mailto:usb-bounces@opencores.org]On Behalf Of Mohammad AK Sent: Monday, March 08, 2004 10:34 AM To: usb@opencores.org Subject: [usb] USB1.1 transceiver hi everybody I would appreciate, any comments on the attached schematic. thanks AbuKhater ---------------------------------------------------------------------------- -- Do you Yahoo!? Yahoo! Search - Find what youre looking for faster. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040308/d86d9aad/attachment.htm

as I saw in the USB2.0 Spesification ( 7.1.1) a pull up resistor should be connected to a 3.6V to D+ so the host can detect it. about Vbus (the 5 V one , am not using it at all), did u mean it this way or did I got u wrong? AbuKhater Marc Reinig mreinig@pacbell.net> wrote: According to the USB spec., you are not supposed to source any current when Vusb is not present. You need to gate your connection between the 3.3 V (J3 - 5) and R10 with Vusb. Marc Reinig System Solutions -----Original Message----- From: usb-bounces@opencores.org [mailto:usb-bounces@opencores.org]On Behalf Of Mohammad AK Sent: Monday, March 08, 2004 10:34 AM To: usb@opencores.org Subject: [usb] USB1.1 transceiver hi everybody I would appreciate, any comments on the attached schematic. thanks AbuKhater --------------------------------- Do you Yahoo!? Yahoo! Search - Find what youre looking for faster._______________________________________________ http://www.opencores.org/mailman/listinfo/usb --------------------------------- Do you Yahoo!? Yahoo! Search - Find what youÂ’re looking for faster. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040309/e2c86407/attachment.htm

I will short resistors connected to MODE and SUSPEND (there is no Suspend as I saw in the USB1.1 Core) about the 10K, actually I am exaggerating it , I may use something like 2.2K, its only for protection in case I had two outputs connected to gether, am new to FPGA :) after all do u think its gona work properly? AbuKhater Rudolf Usselmann rudi@asics.ws> wrote: - Mode should be hard wired - Suspend should go to the FPGA (if you are planning to use it, otherwise hardwire as ell). - Why do you use 10K resistors between the FPGA and the transceiver ? On Tue, 2004-03-09 at 01:34, Mohammad AK wrote: -- rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ http://www.opencores.org/mailman/listinfo/usb --------------------------------- Do you Yahoo!? Yahoo! Search - Find what youÂ’re looking for faster. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040309/0cb42bde/attachment.htm

This is just describing a worst case of a pull down of the 1.5K resistor from 3.3V + 10% = ~3.6V. The point I was trying to make was that you must not source current when Vbus of the host is removed. So if your device is plugged in and your resistor is not gated by Vbus, it will source current to the host. Marc Reinig System Solutions -----Original Message----- From: usb-bounces@opencores.org [mailto:usb-bounces@opencores.org]On Behalf Of M. AbuKhater Sent: Tuesday, March 09, 2004 6:50 AM To: Discussion list about free, open source USB IP core Subject: RE: [usb] USB1.1 transceiver as I saw in the USB2.0 Spesification ( 7.1.1) a pull up resistor should be connected to a 3.6V to D+ so the host can detect it. about Vbus (the 5 V one , am not using it at all), did u mean it this way or did I got u wrong? AbuKhater Marc Reinig mreinig@pacbell.net> wrote: According to the USB spec., you are not supposed to source any current when Vusb is not present. You need to gate your connection between the 3.3 V (J3 - 5) and R10 with Vusb. Marc Reinig System Solutions -----Original Message----- From: usb-bounces@opencores.org [mailto:usb-bounces@opencores.org]On Behalf Of Mohhammad AK Sent: Monday, March 08, 2004 10:34 AM To: usb@opencores.org Subject: [usb] USB1.1 transceiver hi everybody I would appreciate, any comments on the attached schematic. thanks AbuKhater -------------------------------------------------------------------------- Do you Yahoo!? Yahoo! Search - Find what youre looking for faster. _______________________________________________ http://www.opencores.org/mailman/listinfo/usb ---------------------------------------------------------------------------- -- Do you Yahoo!? Yahoo! Search - Find what youre looking for faster. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/usb/attachments/20040309/a20e725f/attachment.htm