Hi all,

I have been trying to make the usb1.1 core work in low speed but
without success. It runs fine in full speed @ 48Mhz clock but it doesn't
repond at low speed (I assume its a 6 Mhz clock we have to use!). I get
no response from the PHY and I guess no low speed logic as been
implemented in it.

I know the J & K state are supposed to be inverted for low speed but
after reading up on the USB1.1 Specification, I'm still not clear weather
it is the job of the HUB or the USB DEVICE to invert the logic.

Any help or hints would be greatly appreciated

Somphong

Hi dear, I have tried this IP at 1.5 Mhz clock I have got the Setup packet Succesfully , but in responce to the next IN token when i m sending the DATA1 its not sending ACK back. Its right that there is no logic written for the LOW SPEED in the TX_PHY module but by slight changes u can do that. thanks regards Govind ----- Original Message ----- From: somphongs at h...somphongs at h...> To: Date: Thu Apr 1 19:10:53 CEST 2004 Subject: [usb] USB1.1 Low Speed Issue---HELP!!

A few things need to be changed for low speed operation, for example the
data lines are inverted (inverting J and K has the same effect). That is
the job of the device. A hub, if present, will expect them to be
correct, and only converts between to/from high speed data in the case
of a high speed hub.

It may be necessary to change some of the mode inputs to the phy chip as
well. From memory, when I modified it for low-speed use, I think I just
changed the clock divider, and still used a 48MHz clock, but that was
probably just because an accurate 48MHz clock was provided by the dev
board we were using. It's been a couple of years since I did this, so
there may be other things which need changing as well. There wasn't much
different though.

Mark.


Govind.sharma5-at-yahoo.co.in |OpenCores| wrote:

Are you implementing into an Altera FPGA? I have not been successful in getting the USB to work but I am implementing in a Xilinx FPGA. Just curious what you did to get the core to work at all? Thanks, Ann -----Original Message----- From: usb-bounces at opencores.org [mailto:usb-bounces at opencores.org]On Behalf Of Govind.sharma5 at yahoo.co.in Sent: Thursday, June 28, 2007 5:20 AM To: usb at opencores.org Subject: Re: [usb] USB1.1 Low Speed Issue---HELP!! Hi dear, I have tried this IP at 1.5 Mhz clock I have got the Setup packet Succesfully , but in responce to the next IN token when i m sending the DATA1 its not sending ACK back. Its right that there is no logic written for the LOW SPEED in the TX_PHY module but by slight changes u can do that. thanks regards Govind ----- Original Message ----- From: somphongs at h...somphongs at h...> To: Date: Thu Apr 1 19:10:53 CEST 2004 Subject: [usb] USB1.1 Low Speed Issue---HELP!! _______________________________________________ http://www.opencores.org/mailman/listinfo/usb