I did a little testing of the USB 2.0 core a while ago, and also
noticed the usb_vbus_pad_i problem. The Verilog code expects
ubs_vbus_pad_i to be a negative true. (don't ask me why, seems incorrect
to me) So, you can either tie it off low, or invert it once it comes
into your chip. (I did the latter)

I also noticed that there is something strange with the millisecond
"T1" timers in usbf_utmi_ls.v. (T1_st_3_0_mS, T1_gt_3_0_mS, etc) There
are two counters used to calculate time:

ps_cnt : increments every clock cycle (16.7ns), resets after 15
cycles. (15*16.7ns=250 ns)

idle_cnt1 : increments when ps_cnt resets (250 ns), resets after 250
cycles (250*250ns=62.5us)

Now take T1_gt_3_0_mS for example. If I understand the naming
convention correctly, we want this counter to go high after ~3.0mS.
According to the logic in usbf_utmi_ls.v it will go high when (idle_cnt1
USBF_T1_C_3_0_MS is only defined as 48. (48*250ns=12us) If you look the comments where USBF_T1_C_3_0_MS is defined, it looks like USBF_T1_C_3_0_MS was expecting to be based off of 62.5us counter. (not the 250ns counter, idle_cnt1) So, in my design I created an idle_cnt2 that incremented every 62.5us, and used that as the counter for T1_st_3_0_mS, T1_gt_3_0_mS, T1_gt_3_125_mS, and T1_gt_5_0_mS. My lingering questions were: What should I use to reset this counter and what should its upper bound be. As it stands now I use... reg [7:0] idle_cnt2, idle_cnt2_next = 8'h0; // Count 62.5 uS always @(posedge clk) if(!idle_long || idle_cnt_clr) idle_cnt2 usb-bounces@opencores.org [mailto:usb-bounces@opencores.org] On Behalf Of dmakwana@slscorp.com Sent: Thursday, May 27, 2004 5:00 AM To: usb@opencores.org Subject: Re: [usb] Ask a help on Dear Mr. NI haiqiao, Yes, you are true, even I have found the same thing during hardware testing of the USB2.0 IP. The only solution to this is just to hardcode the usb_vbus_pad_i signal to "0". Currently I am in stage of testing the core and I was suceessfully passed the Speed Negotiation phase and the host perfectly responded for High Speed device with Chirp KJKJKJ sequence, and after that I am also geting SOF command in high speed mode, but them some thing happens to the core and I am not getting SETUP command for "Get Descriptor". Please help me if have passed the Enumeration pahse for USB2.0 IP. Thanks & Regards Deepak Makwana dmakwana@slscorp.com ----- Original Message ----- From: nihq@r... To: usb@o... Date: Sun, 12 Jan 2003 04:52:08 -0100 Subject: [usb] Ask a help on _______________________________________________ http://www.opencores.org/mailman/listinfo/usb

On Fri, 2004-05-28 at 01:12, Brian Adams wrote:


[SNIP]

Hi Guys, I am in the process of rewriting major portions of the USB 2.0 Device IP. This will take a while. The goal is to build a FPGA prototype and take it through USB certification as well. Brian form SMSC was kind enough to donate a very nice PHY from SMSC, the GT3200. It is a fully UTMI complaint PHY. Since I'm doing everything alone this will take time. Perhaps somebody would like to help with a test-bench ? You must be serious about it - it takes a lot of time and work. I can provide a lot of guidance. The New version of the core will be release under a NEW LICENSE. It will now be free ONLY for Educational and Personal uses. It still will be Open Source. Reason for that is that I am not getting any help at all. From the 10(+/-) people who offered to write a test bench in the last 3 years, NOBODY ever did. I will not release my own test bench - don't even bother asking. I can't handle the tech support for the core, I'm not going to do the same with the test bench. All requests for the test bench will be redirected to /dev/null. Sorry, no other way here ... If you guys find any bugs, please email (or cc) them to me directly as well. Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/