Hello Rudi,

I was going through the code to get a better understanding and to add
low-speed option. I got to the Packet Disassembler and I have a few
questions.

1.) All the #1 - I assume are for simulation knowing that the synthesis
tool will remove these.
2.) In the state machine you have no else statements for your ifs. Are
you assuming that the synthesis tool will optimize and will assume the
else is the current state?
3.) You did not define all variable in all states. For example once
pid_ack gets set in the ACTIVE state do you again assume the
synthesis tool will optimize and clear the signal in the IDLE condition?

My guess is that this is coding style. I got burned by an old tool once
and now I assign all variables in all states to be safe. My personal belt
and suspenders approach.

erich

On Fri, 2004-06-25 at 03:39, k1e3c1@hotmail.com wrote:

Yes thats correct.



Nothing to do wit synthesis. Default values are provided
for all variables. There is no need to assign each variable
in each state or provide "else" clause. There are many good
books on verilog, I suggest you pick one up that explains
this subject in greater detail.

Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/