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timeout by Unknown on Jun 29, 2004			Not available!
Hi, I would like to ask about timeout values in usb 2.0 core, why these are 622 ns FS(7.5b times) and 400 ns HS (192b times)? Shouldn't these be 18 bit times in FS and 816 bit times in HS as stated in 7.1.18 of usb spec (end to end delay)? And how timeout is checked? Is timeout counter started when linestate enters squelch level (or SE0 to J transition for FS) and reset when linestate leaves squelch (or J to K transition for FS), when device waits for data or response from usb host)? Hi, I would like to ask about timeout values in usb 2.0 core, why these are 622 ns FS(7.5b times) and 400 ns HS (192b times)? Shouldn't these be 18 bit times in FS and 816 bit times in HS as stated in 7.1.18 of usb spec (end to end delay)? And how timeout is checked? Is timeout counter started when linestate enters squelch level (or SE0 to J transition for FS) and reset when linestate leaves squelch (or J to K transition for FS), when device waits for data or response from usb host)?

timeout by Unknown on Aug 16, 2004			Not available!
hi, U need to recheck the specifications, The specifications specify a time out of 7.5bit times and 192bit times only and not 18 and 816. The second part of Q, The reset is done only at the starting of the device setup and there will be J and K ie both D+ and D- high for 10 milliseconds. The time out thing, i feel that there is counter used rather than SE0 to J transistion ,as the SEO to J transistion is used to give a wakeup signal to a device. If u find something different, do enlighten me with it. regards pranav ----- Original Message ----- From: <A HREF="mailto:rtl2gds@S...">rtl2gds@S...</A><<A HREF="mailto:rtl2gds@S...">rtl2gds@S...</A>> To: Date: Tue Jun 29 22:58:14 CEST 2004 Subject: [usb] timeout [q] Hi, I would like to ask about timeout values in usb 2.0 core, why these are 622 ns FS(7.5b times) and 400 ns HS (192b times)? Shouldn't these be 18 bit times in FS and 816 bit times in HS as stated in 7.1.18 of usb spec (end to end delay)? And how timeout is checked? Is timeout counter started when linestate enters squelch level (or SE0 to J transition for FS) and reset when linestate leaves squelch (or J to K transition for FS), when device waits for data or response from usb host)? [/q] hi, U need to recheck the specifications, The specifications specify a time out of 7.5bit times and 192bit times only and not 18 and 816. The second part of Q, The reset is done only at the starting of the device setup and there will be J and K ie both D+ and D- high for 10 milliseconds. The time out thing, i feel that there is counter used rather than SE0 to J transistion ,as the SEO to J transistion is used to give a wakeup signal to a device. If u find something different, do enlighten me with it. regards pranav ----- Original Message ----- From: rtl2gds@S...rtl2gds@S...> To: Date: Tue Jun 29 22:58:14 CEST 2004 Subject: [usb] timeout Hi, I would like to ask about timeout values in usb 2.0 core, why these are 622 ns FS(7.5b times) and 400 ns HS (192b times)? Shouldn't these be 18 bit times in FS and 816 bit times in HS as stated in 7.1.18 of usb spec (end to end delay)? And how timeout is checked? Is timeout counter started when linestate enters squelch level (or SE0 to J transition for FS) and reset when linestate leaves squelch (or J to K transition for FS), when device waits for data or response from usb host)?

timeout by Unknown on Aug 16, 2004			Not available!
hi sorry,I made a mistake. The delay specified to each is 7.5 bit times, hence a total of 15bit times, plus a delay of 2 bit times give a total of 17 bit times, Hence there is a delay of not more than 18bit times was specified. Hence the specification is 7.5 bit times only and this will reflect the same for the High speed. The SEO to J transistion is for EOP and not for resetting, but i couldnot properly connect your question with the SE0 to J tansistion. pranav ----- Original Message ----- From: <A HREF="mailto:rtl2gds@S...">rtl2gds@S...</A><<A HREF="mailto:rtl2gds@S...">rtl2gds@S...</A>> To: Date: Tue Jun 29 22:58:14 CEST 2004 Subject: [usb] timeout [q] Hi, I would like to ask about timeout values in usb 2.0 core, why these are 622 ns FS(7.5b times) and 400 ns HS (192b times)? Shouldn't these be 18 bit times in FS and 816 bit times in HS as stated in 7.1.18 of usb spec (end to end delay)? And how timeout is checked? Is timeout counter started when linestate enters squelch level (or SE0 to J transition for FS) and reset when linestate leaves squelch (or J to K transition for FS), when device waits for data or response from usb host)? [/q] hi sorry,I made a mistake. The delay specified to each is 7.5 bit times, hence a total of 15bit times, plus a delay of 2 bit times give a total of 17 bit times, Hence there is a delay of not more than 18bit times was specified. Hence the specification is 7.5 bit times only and this will reflect the same for the High speed. The SEO to J transistion is for EOP and not for resetting, but i couldnot properly connect your question with the SE0 to J tansistion. pranav ----- Original Message ----- From: rtl2gds@S...rtl2gds@S...> To: Date: Tue Jun 29 22:58:14 CEST 2004 Subject: [usb] timeout Hi, I would like to ask about timeout values in usb 2.0 core, why these are 622 ns FS(7.5b times) and 400 ns HS (192b times)? Shouldn't these be 18 bit times in FS and 816 bit times in HS as stated in 7.1.18 of usb spec (end to end delay)? And how timeout is checked? Is timeout counter started when linestate enters squelch level (or SE0 to J transition for FS) and reset when linestate leaves squelch (or J to K transition for FS), when device waits for data or response from usb host)?

timeout by Unknown on Aug 26, 2004			Not available!
[q] The delay specified to each is 7.5 bit times, hence a total of 15bit times, plus a delay of 2 bit times give a total of 17 bit times, Hence there is a delay of not more than 18bit times was specified. Hence the specification is 7.5 bit times only and this will reflect the same for the High speed. The SEO to J transistion is for EOP and not for resetting, but i couldnot properly connect your question with the SE0 to J tansistion. pranav [/q] Hi, I mean resetting/starting timeout timer not USB reset. I understand spec like that: For eg. when device receives setup token in control transfer it expects data0 packet to arrive before timeout after setup token(18 bit times for Full Speed). So, it starts timeout timer after succesfull reception of SETUP (ie after EOP = SE0 to J transition) and check if timout occurs. I am not sure, but timeout timer maybe should be set to value 18 bit times minus SETUP packet length duration time in this example, because timer starts after SETUP packet is received. Am i right? Michal [q]> I would like to ask about timeout values in usb 2.0 core, why [/q] these [q]> are > 622 ns FS(7.5b times) and 400 ns HS (192b times)? > Shouldn't these be 18 bit times in FS and 816 bit times in HS [/q] as [q]> stated > in 7.1.18 of usb spec (end to end delay)? > And how timeout is checked? Is timeout counter started when > linestate > enters squelch level (or SE0 to J transition for FS) and reset [/q] when [q]> linestate leaves squelch (or J to K transition for FS), when [/q] device [q]> waits > for data or response from usb host)? > > [/q] [/q] The delay specified to each is 7.5 bit times, hence a total of 15bit times, plus a delay of 2 bit times give a total of 17 bit times, Hence there is a delay of not more than 18bit times was specified. Hence the specification is 7.5 bit times only and this will reflect the same for the High speed. The SEO to J transistion is for EOP and not for resetting, but i couldnot properly connect your question with the SE0 to J tansistion. pranav Hi, I mean resetting/starting timeout timer not USB reset. I understand spec like that: For eg. when device receives setup token in control transfer it expects data0 packet to arrive before timeout after setup token(18 bit times for Full Speed). So, it starts timeout timer after succesfull reception of SETUP (ie after EOP = SE0 to J transition) and check if timout occurs. I am not sure, but timeout timer maybe should be set to value 18 bit times minus SETUP packet length duration time in this example, because timer starts after SETUP packet is received. Am i right? Michal > I would like to ask about timeout values in usb 2.0 core, why these > are > 622 ns FS(7.5b times) and 400 ns HS (192b times)? > Shouldn't these be 18 bit times in FS and 816 bit times in HS as > stated > in 7.1.18 of usb spec (end to end delay)? > And how timeout is checked? Is timeout counter started when > linestate > enters squelch level (or SE0 to J transition for FS) and reset when > linestate leaves squelch (or J to K transition for FS), when device > waits > for data or response from usb host)? > >

timeout by pranavkumar on Aug 27, 2004			pranavkumar Posts: 3 Joined: Oct 9, 2010 Last seen: Jan 8, 2025
hi michal, I think this might help you. For full-/low-speed transactions, the timer starts counting on the SE0-to-Â‘JÂ’ transition of the EOP strobe and stops counting when the Idle-to-Â‘KÂ’ SOP transition is detected. For high-speed transactions, the timer starts counting when the data lines return to the squelch level and stops counting when the data lines leave the squelch level. If a response is not received within this worst case timeout(18 bit timres for FS), then the transmitter considers that the packet transmission has failed. Then the concerned register bit is changed and the next Token packet is sent. pranav [q] Hi, I mean resetting/starting timeout timer not USB reset. I understand spec like that: For eg. when device receives setup token in control transfer it expects data0 packet to arrive before timeout after setup token(18 bit times for Full Speed). So, it starts timeout timer after succesfull reception of SETUP (ie after EOP = SE0 to J transition) and check if timout occurs. I am not sure, but timeout timer maybe should be set to value 18 bit times minus SETUP packet length duration time in this example, because timer starts after SETUP packet is received. Am i right? Michal [q] > I would like to ask about timeout values in usb[/q] 2.0 core, why [q]> these [q] > are > 622 ns FS(7.5b times) and 400 ns HS (192b[/q] times)? [q] > Shouldn't these be 18 bit times in FS and 816[/q] bit times in HS [q]> as [q] > stated > in 7.1.18 of usb spec (end to end delay)? > And how timeout is checked? Is timeout counter[/q] started when [q] > linestate > enters squelch level (or SE0 to J transition for[/q] FS) and reset [q]> when [q] > linestate leaves squelch (or J to K transition[/q] for FS), when [q]> device [q] > waits > for data or response from usb host)? > > [/q] > > [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/usb">http://www.opencores.org/mailman/listinfo/usb</A> [/q] __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around <A HREF="http://mail.yahoo.com">http://mail.yahoo.com</A> hi michal, I think this might help you. For full-/low-speed transactions, the timer starts counting on the SE0-to-Â‘JÂ’ transition of the EOP strobe and stops counting when the Idle-to-Â‘KÂ’ SOP transition is detected. For high-speed transactions, the timer starts counting when the data lines return to the squelch level and stops counting when the data lines leave the squelch level. If a response is not received within this worst case timeout(18 bit timres for FS), then the transmitter considers that the packet transmission has failed. Then the concerned register bit is changed and the next Token packet is sent. pranav Hi, I mean resetting/starting timeout timer not USB reset. I understand spec like that: For eg. when device receives setup token in control transfer it expects data0 packet to arrive before timeout after setup token(18 bit times for Full Speed). So, it starts timeout timer after succesfull reception of SETUP (ie after EOP = SE0 to J transition) and check if timout occurs. I am not sure, but timeout timer maybe should be set to value 18 bit times minus SETUP packet length duration time in this example, because timer starts after SETUP packet is received. Am i right? Michal > I would like to ask about timeout values in usb 2.0 core, why > these > are > 622 ns FS(7.5b times) and 400 ns HS (192b times)? > Shouldn't these be 18 bit times in FS and 816 bit times in HS > as > stated > in 7.1.18 of usb spec (end to end delay)? > And how timeout is checked? Is timeout counter started when > linestate > enters squelch level (or SE0 to J transition for FS) and reset > when > linestate leaves squelch (or J to K transition for FS), when > device > waits > for data or response from usb host)? > > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/usb __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

timeout by Unknown on Sep 5, 2004			Not available!
Hi Pranav, Big thanks for your response, now I understand. Michal ----- Original Message ----- From: pranav kumar<<A HREF="mailto:pranav_c_java@y...">pranav_c_java@y...</A>> To: Date: Fri Aug 27 12:25:21 CEST 2004 Subject: [usb] timeout [q] hi michal, I think this might help you. For full-/low-speed transactions, the timer starts counting on the SE0-to-Â‘JÂ’ transition of the EOP strobe and stops counting when the Idle-to-Â‘KÂ’ SOP transition is detected. For high-speed transactions, the timer starts counting when the data lines return to the squelch level and stops counting when the data lines leave the squelch level. If a response is not received within this worst case timeout(18 bit timres for FS), then the transmitter considers that the packet transmission has failed. Then the concerned register bit is changed and the next Token packet is sent. pranav [q]> Hi, > I mean resetting/starting timeout timer not USB > reset. > I understand spec like that: > For eg. when device receives setup token in control > transfer it expects > data0 packet to arrive before timeout after setup > token(18 bit times for > Full Speed). So, it starts timeout timer after > succesfull reception of > SETUP (ie after EOP = SE0 to J transition) and check > if timout occurs. > > I am not sure, but timeout timer maybe should be set > to value 18 bit > times minus SETUP packet length duration time in > this example, because > timer starts after SETUP packet is received. > Am i right? > > Michal > > > [q]> > I would like to ask about timeout values in usb [/q] > 2.0 core, why [q] > these [q]> > are > > 622 ns FS(7.5b times) and 400 ns HS (192b [/q] > times)? [q]> > Shouldn't these be 18 bit times in FS and 816 [/q] > bit times in HS [q] > as [q]> > stated > > in 7.1.18 of usb spec (end to end delay)? > > And how timeout is checked? Is timeout counter [/q] > started when [q]> > linestate > > enters squelch level (or SE0 to J transition for [/q] > FS) and reset [q] > when [q]> > linestate leaves squelch (or J to K transition [/q] > for FS), when [q] > device [q]> > waits > > for data or response from usb host)? > > > > [/q] > > [/q] > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/usb">http://www.opencores.org/mailman/listinfo/usb</A> > [/q] __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around <A HREF="http://mail.yahoo.com">http://mail.yahoo.com</A> [/q] Hi Pranav, Big thanks for your response, now I understand. Michal ----- Original Message ----- From: pranav kumarpranav_c_java@y...> To: Date: Fri Aug 27 12:25:21 CEST 2004 Subject: [usb] timeout hi michal, I think this might help you. For full-/low-speed transactions, the timer starts counting on the SE0-to-Â‘JÂ’ transition of the EOP strobe and stops counting when the Idle-to-Â‘KÂ’ SOP transition is detected. For high-speed transactions, the timer starts counting when the data lines return to the squelch level and stops counting when the data lines leave the squelch level. If a response is not received within this worst case timeout(18 bit timres for FS), then the transmitter considers that the packet transmission has failed. Then the concerned register bit is changed and the next Token packet is sent. pranav > Hi, > I mean resetting/starting timeout timer not USB > reset. > I understand spec like that: > For eg. when device receives setup token in control > transfer it expects > data0 packet to arrive before timeout after setup > token(18 bit times for > Full Speed). So, it starts timeout timer after > succesfull reception of > SETUP (ie after EOP = SE0 to J transition) and check > if timout occurs. > > I am not sure, but timeout timer maybe should be set > to value 18 bit > times minus SETUP packet length duration time in > this example, because > timer starts after SETUP packet is received. > Am i right? > > Michal > > > > > I would like to ask about timeout values in usb > 2.0 core, why > these > > are > > 622 ns FS(7.5b times) and 400 ns HS (192b > times)? > > Shouldn't these be 18 bit times in FS and 816 > bit times in HS > as > > stated > > in 7.1.18 of usb spec (end to end delay)? > > And how timeout is checked? Is timeout counter > started when > > linestate > > enters squelch level (or SE0 to J transition for > FS) and reset > when > > linestate leaves squelch (or J to K transition > for FS), when > device > > waits > > for data or response from usb host)? > > > > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/usb > __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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