Could anybody give me an approximate gate count for the USB 1.1 PHY
and FUNCTION implementation. I am a bit worried that with so much of
the protocol implemented in hardware, it just might be too large for my
use.

Using quartus and Altera silicon with 1 Bulk endpoint in both directions gives Logic cells 1002 registers 501 Memory bits 2048 (usb1_rom1 implemented as ROM uses 1024, + 2x512 bits for each of the endpoint 0 FIFOs) Matt -----Original Message----- From: usb-bounces@opencores.org [mailto:usb-bounces@opencores.org] On Behalf Of pdrand@online.no Sent: 17 October 2004 16:40 To: usb@opencores.org Subject: [usb] USB 1.1 gate count Could anybody give me an approximate gate count for the USB 1.1 PHY and FUNCTION implementation. I am a bit worried that with so much of the protocol implemented in hardware, it just might be too large for my use. _______________________________________________ http://www.opencores.org/mailman/listinfo/usb