According to spec EOP is SE0 for approximately 2 bit times followed by a J for 1 bit time. I saw that the EOP is only one clock time. I would like to suggest a fix by adding a state in processTxByte.v. ////////////////////////////////////////////////////////////////////// //// //// //// processTxByte //// //// //// This file is part of the usbhostslave opencores effort. //// http://www.opencores.org/cores/usbhostslave/ //// //// //// //// Module Description: //// //// //// //// //// To Do: //// //// //// //// //// Author(s): //// //// - Steve Fielding, sfielding@base2designs.com //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // $Id: processTxByte.v,v 1.3 2004/12/31 14:40:43 sfielding Exp $ // // CVS Revision History // // $Log: processTxByte.v,v $ // Revision 1.3 2004/12/31 14:40:43 sfielding // Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME // // `timescale 1ns / 1ps `include "usbSerialInterfaceEngine_h.v" `include "usbConstants_h.v" module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn); input clk; input [1:0]JBit; input [1:0]KBit; input processTxByteWEn; input rst; input [7:0]TxByteCtrlIn; input [7:0]TxByteIn; input USBWireGnt; input USBWireRdy; output processTxByteRdy; output USBWireCtrl; output [1:0]USBWireData; output USBWireReq; output USBWireWEn; wire clk; wire [1:0]JBit; wire [1:0]KBit; reg processTxByteRdy, next_processTxByteRdy; wire processTxByteWEn; wire rst; wire [7:0]TxByteCtrlIn; wire [7:0]TxByteIn; reg USBWireCtrl, next_USBWireCtrl; reg [1:0]USBWireData, next_USBWireData; wire USBWireGnt; wire USBWireRdy; reg USBWireReq, next_USBWireReq; reg USBWireWEn, next_USBWireWEn; // diagram signals declarations reg [3:0]i, next_i; reg [7:0]TxByte, next_TxByte; reg [7:0]TxByteCtrl, next_TxByteCtrl; reg [1:0]TXLineState, next_TXLineState; reg [3:0]TXOneCount, next_TXOneCount; // BINARY ENCODED state machine: prcTxB // State codes definitions: `define START_PTBY 4'b0000 `define PTBY_WAIT_EN 4'b0001 `define SEND_BYTE_UPDATE_BYTE 4'b0010 `define SEND_BYTE_WAIT_RDY 4'b0011 `define SEND_BYTE_CHK 4'b0100 `define SEND_BYTE_BIT_STUFF 4'b0101 `define SEND_BYTE_WAIT_RDY2 4'b0110 `define SEND_BYTE_CHK_FIN 4'b0111 `define PTBY_WAIT_GNT 4'b1000 //by PK `define STOP_SND_SE0_3 4'b1111 //by PK `define STOP_SND_SE0_2 4'b1001 `define STOP_SND_SE0_1 4'b1010 `define STOP_CHK 4'b1011 `define STOP_SND_J 4'b1100 `define STOP_SND_IDLE 4'b1101 `define STOP_FIN 4'b1110 reg [3:0]CurrState_prcTxB, NextState_prcTxB; // Machine: prcTxB // NextState logic (combinatorial) always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB) begin NextState_prcTxB