Hi,

I am trying to synthesize the USB 1.1 core with synopsys design
compiler. The netlist is ok and the log file doesn't show any timing
violations. However, when I put the netlist to Modelsim for post-
synthesis verification, Modelsim gives a huge amount of HOLD
VIOLATIONs and SETUP VIOLATIONs. Here is an example:

# ** Warning: */DF8L HOLD Low VIOLATION ON D WITH RESPECT TO C;
# Expected := 2.01 ns; Observed := 0.41 ns; At : 198.39 ns
# Time: 198390 ps Iteration: 0
Instance: /test/mydesign/u0xphyxi_rx_phyxdpll_state_regx0x

The SETUP VIOLATIONs are followed by the HOLD VIOLATIONs and it
looks like the initial HOLD VIOLATION causes the following VIOLATIONS.

What I did is synthesize the usb core and the USB physical layer
(usb_phy) seperately, and use the testbench (from opencores) to do
the test. The result was NOT successful due to the timing violations.

Maybe the script file I use is NOT sophisticated enough. At least it has
the period (1/48 MHz) and input/output delays (1.5 ns).

Someone knows how to fix that problem? Thanks a lot and looking
forward to your opinions.

Jason