I'm currently using the USB 2.0 function core attached to the USB 1.1
UTMI interface in order to connect it to a USB 1.1 phy (don't ask).

I have replaced the external SRAM port with an internal BRAM as well
as replaced the WB interface with an OPB interface (wrapper just
wasn't treating me right).

I have been successfully using this configuration in a variety of
different modes, and I recently encountered some trouble. Just to give
you an idea of the working portion of the core, I have a Linux file
backed storage gadget driver ported for this core (it works quite
well). So I've been performing thousands of transactions on CTRL
endpoints as well as INTERRUPT and BULK endpoints. I feel pretty good
about the new register interface and with the BRAM addition.

I have found that when using an endpoint (BULK or CTRL as OUT) with
either single or double buffering (of course single for CTRL, but with
single or double for BULK) (no DMA) enabled, that after the buffer
space has been used, the core does not respond with NAKs consistently.
Not only does it not respond with NAKs consistently, but it quickly
stops responding to all traffic. It will NAK between 0 and 3 packets
before it stops respoding completely.

Looking at the protocol engine state machine, it seems pretty simple,
once the used bit is set for buf0 and buf1, the core should NAK
packets until a reset. This is not what I am seeing. The behavior only
appears to affect OUT transactions.

Has anyone seen this behavior? Any help that can be offered would be
much appreciated.