Hi,

I'm trying to get the usbHostSlave core working on a custom system of
the following:

Cyclone FPGA
SDRAM running at 50 Mhz (from PLL)
48MHz clock -> PLL -> usb_clk
NIOS II Eval
USB1T11AM PHY (1 for host, 1 for slave) - I beleive this is
similar/the same to the phillips one

Basically, I have the same schematic as the daughtercard interface
presented in the project zip file, and I'm trying to get any of the
Quartus examples to work (loopback test, simple host, simple slave)..
I have been unsuccessful so far unfortunately. I doubt it's the
hardware since it's quite simple in nature. One question I have is
that could there be a problem with using two different clocks in NIOS?
I have my core clk at 50MHz, and then another clock defined at 48Mhz
only for the USB. Could this be a potential problem? It would be a
pain to change my whole system around to 48Mhz, so I tried to keep it
this way...

Also, should anything be done with the TICK outputs? Right now, I
don't have them going anywhere.

Lastly, are there some quick tests I could do to verify anything...
ie: looping back inside the FPGA instead of on the board to eliminate
hardware... I'm not too familiar with the physical interface of USB,
so I do'nt know what is and isn't possible. Any help would be
appreciated!

Thank you,

Jai