In simulating the USB core, it looks like bit 3 and 4 of the Endpoint
Interrupt Registers are swapped. When I send my 1st setup packet to
the controller, I get an interrupt for buffer 1 instead of buffer 0.
The write is directed to buffer 0, but the buffer 1 interrupt is
asserted instead of the buffer 0 interrupt.

In the file usbf_pe.v, there's a section of code:
// Select buffer: buf_sel==0 buffer0; buf_sel==1 buffer1
assign buf_sel = dma_en ? 1'b0 : CTRL_ep ? in_token : ((uc_bsel[0]
| buf0_na) & !buf1_na);

This seems to make sense - buf_sel is low for buffer 0, high for buffer 1.

BUT... later on, the buffer full/empty bits are set by the following code:
assign int_buf1_set = !buf_sel & buffer_done & int_set_en &
!buf1_not_aloc;
assign int_buf0_set = buf_sel & buffer_done & int_set_en &
!buf0_not_aloc;

Note that int_buf1_set is asserted when buf_sel is low.

John Providenza